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Method for preparing ultra-thin copper seed crystal layer on diffusion barrier layer and application thereof

A technology of copper seed layer and barrier layer, which is applied in coating, metal material coating process, semiconductor/solid-state device manufacturing, etc., can solve problems such as difficult film uniformity, improve performance and reliability, increase precision Effect of ability to control, ability to improve

Inactive Publication Date: 2014-02-12
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005]At present, magnetron sputtering technology is mainly used in the industry to prepare diffusion barrier layer and copper seed layer, but it is difficult to fill holes and trenches with high aspect ratio To ensure the uniformity of the film, it is very important to develop a new process for preparing a diffusion barrier layer and a copper seed layer for the development of modern integrated circuits. At present, Atomic Layer Deposition (ALD) has great potential

Method used

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  • Method for preparing ultra-thin copper seed crystal layer on diffusion barrier layer and application thereof
  • Method for preparing ultra-thin copper seed crystal layer on diffusion barrier layer and application thereof
  • Method for preparing ultra-thin copper seed crystal layer on diffusion barrier layer and application thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0041] The copper interconnect structure is prepared as follows:

[0042] Step A. If figure 1As shown, on the substrates 201 and 202 after any layer of an interconnection structure is wired, an etch stop layer 203 is deposited first, and then an insulating dielectric layer 204 is deposited.

[0043] The material of the insulating dielectric layer 204 is silicon dioxide SiO 2 , the material of the etch stop layer 203 is silicon nitride.

[0044] Step B. If figure 1 As shown, the interconnected trenches are formed by photolithographic etching using a standard dual damascene process flow.

[0045] Step C. If figure 2 As shown, the Ta / TaN diffusion barrier layer 205 is deposited by magnetron sputtering.

[0046] Step D. If image 3 As shown, an ultra-thin copper seed layer 206 is prepared on the barrier layer by atomic layer deposition.

[0047] The precursors for depositing the ultra-thin copper seed layer are bis(hexafluoroacetylacetonate) copper and diethyl zinc, and th...

Embodiment 2

[0056] The copper interconnect structure is prepared as follows:

[0057] Step A. If figure 1 As shown, on the substrates 201 and 202 after any layer of an interconnection structure is wired, an etch stop layer 203 is deposited first, and then an insulating dielectric layer 204 is deposited.

[0058] The material of the insulating dielectric layer 204 is silicon dioxide SiO 2 , the material of the etch stop layer 203 is silicon nitride.

[0059] Step B. If figure 1 As shown, the interconnected trenches are formed by photolithographic etching using a standard dual damascene process flow.

[0060] Step C. If figure 2 As shown, the Ta / TaN diffusion barrier layer 205 is deposited by magnetron sputtering.

[0061] Step D. If image 3 As shown, an ultra-thin copper seed layer 206 is prepared on the barrier layer by atomic layer deposition.

[0062] The precursors for depositing the ultra-thin copper seed layer are bis(hexafluoroacetylacetonate) copper and diethyl zinc, and t...

Embodiment 3

[0071] The copper interconnect structure is prepared as follows:

[0072] Step A. If figure 1 As shown, on the substrates 201 and 202 after any layer of an interconnection structure is wired, an etch stop layer 203 is deposited first, and then an insulating dielectric layer 204 is deposited.

[0073] The material of the insulating dielectric layer 201 is fluorinated silicon dioxide SiOF, and the material of the etching stop layer is silicon nitride.

[0074] Step B. If figure 1 As shown, photolithographic etching forms interconnected trenches 210 .

[0075] Step C. If figure 2 As shown, the Ta / TaN diffusion barrier layer 205 is deposited by magnetron sputtering.

[0076] Step D. If image 3 As shown, an ultra-thin copper seed layer 206 is prepared on the barrier layer by atomic layer deposition.

[0077] The precursors for depositing the ultra-thin copper seed layer are bis(hexafluoroacetylacetonate) copper and diethyl zinc, and the bis(hexafluoroacetylacetonate) copper...

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Abstract

The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a method for preparing an ultra-thin copper seed crystal layer on a diffusion barrier layer and an application thereof. According to the method, an atomic layer deposition method is used for preparing the ultra-thin copper seed crystal layer, and the method includes the following steps that Cu (C5HF6O2)2 is adsorbed on the diffusion barrier layer, and the air flow is 100-500 standard milliliter per minute; diethylzinc is adsorbed on the diffusion barrier layer, and the air flow is 100-500 standard milliliter per minute. The method has the advantages that the ALD method is adopted for growing the copper seed crystal layer, under a lower process temperature, only a film with the thickness about 0.02-1nm is formed in each growth cycle, the thickness of the copper seed crystal layer can be effectively controlled, the groove filling performance is good, the adhesion property of electroplated copper and the copper seed crystal layer is improved, the reliability of the method in the integrated circuit copper interconnection application is maintained, and the method provides an ideal interconnection technology solution to technology nodes with the thickness below 22nm.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a manufacturing method and application of an ultra-thin copper seed layer on a diffusion barrier layer. Background technique [0002] With the development of very large-scale integration (VLSI) and ultra-large-scale integration (ULSI), the degree of integration continues to increase, and circuit components are becoming denser. Chip interconnection has become a key factor affecting chip performance. However, the scaling down of interconnect lines in VLSI and ULSI technologies has placed additional demands on processing capabilities due to size constraints of the circuitry. Such requirements include precise machining of multi-layered, high-aspect-ratio structural features. The reliability of these interconnect structures plays a very important role in the success of VLSI and ULSI and the improvement of circuit density. [0003] A...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/3205C23C14/24
CPCH01L21/76877C23C16/45525H01L21/02225H01L21/76802H01L21/76838
Inventor 卢红亮耿阳杨雯孙清清张卫
Owner FUDAN UNIV
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