A kind of fabrication method of germanium nanowire stack structure

Abstract

The invention discloses a manufacturing method of a germanium nano wire laminated structure. The method comprises the following steps: alternately extending single crystal germanium-silicon layers and germanium layers on the surface of a single crystal substrate, and photoengraving and sculpturing the germanium-silicon layers and the germanium layers so as to obtain a germanium-silicon / germanium linear periodic structure; oxidizing the germanium-silicon / germanium linear periodic structure under the atmosphere of pure oxygen, wherein germanium components in the germanium silicon layer are selectively oxidized into germanium dioxide, and meanwhile germanium components in the germanium silicon layer is isolated into the germanium layer; selectively sculpturing by use of hydrofluoric acid and dissolving silicon dioxide, so as to obtain the germanium nano wire laminated structure. The manufacturing method of the germanium nano wire laminated structure has the advantages of large growth area, simple and convenient process, controllable nano wire diameter, low preparation cost and the like.

Description

technical field [0001] The invention relates to the technical field of semiconductor integration, in particular to a method for manufacturing a germanium nanowire stack structure. Background technique [0002] As the core and foundation of the information industry, semiconductor technology is an important symbol to measure a country's scientific and technological progress and comprehensive national strength. In the past 40 years, silicon-based integration technology has followed Moore's law to increase the working speed of devices, increase integration and reduce costs by reducing the feature size of devices. The feature size of silicon-based CMOS devices has been reduced from micrometers to nanometers. However, when the gate length of MOS devices is reduced to less than 90 nanometers, the thickness of the gate dielectric (silicon dioxide) has been gradually reduced to close to 1 nanometer, and physical limitations such as increased off-state leakage, increased power consump...

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Problems solved by technology

However, when the gate length of MOS devices is reduced to less than 90 nanometers, the thickness of the gate dielectric (silicon dioxide) has been gradually reduced to close to 1 nanometer, and physical limitations such as increased off-state leakage, increased power consumption density, and mobility degradation make the device Performance deterioration, traditional silicon-based microelectronics integration technology begins to face dual challenges from physics and technology

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