A Method for Improving Planarization of Superjunction Deep Trench Epitaxial Layers

Abstract

The invention discloses a method for improving super junction deep trench epitaxial layer flattening. The method comprises the steps of (1) depositing an oxide film or a nitride film on the surface of a silicon chip to be a barrier layer, (2) carrying out the etching of a deep trench on the silicon chip, (3) using monocrystalline silicon or polycrystalline silicon to fill the deep trench, and (4) using the chemical and mechanical grinding processes to carry out flattening treatment on the surface of the silicon chip. The step (4) comprises the following steps of (A) grinding an epitaxial layer to remove a half of the epitaxial layer above a barrier layer through the mode of chemical and mechanical grinding and covering a groove by the residue of the chemical and mechanical grinding, (B) after a half of grinding amount is completed, a grinding head is raised, a large amount of deionized water at normal temperature is used to wash the silicon chip and a grinding pad, and the residue of the chemical and mechanical grinding in the groove is removed, and (C) removing the epitaxial layer above the barrier layer totally. According to the method, the epitaxial layer above the barrier layer can be effectively removed so as to improve the super junction epitaxial layer flattening effect.

Description

technical field [0001] The invention belongs to a semiconductor process method in a semiconductor integrated circuit, in particular to a method for improving the planarization of a super junction deep trench epitaxial layer. Background technique [0002] In today's semiconductor technology, deep trench structures are widely used. For example, it is used as an isolation structure to isolate electronic devices with different operating voltages, and it is used in super junction structure semiconductor devices as a P-N junction to achieve high breakdown voltage performance through charge balance in the depletion state, etc. For the method of etching and filling deep trenches in the manufacturing process of the latter super junction metal oxide semiconductor field effect transistor (super junction MOS transistor), an n-type epitaxial layer (single layer) is grown on an n+ type silicon substrate. crystalline silicon), and then etch deep trenches on the epitaxial layer, then selec...

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Problems solved by technology

[0003] In the above method, the selective filling of the deep groove will result in a higher surface step height (about 3 microns), the corresponding grinding time will be longer, and the temperature of the polishing pad will increase abnormally. The residue on the pad will increase dramatically. If the slurry residue in the groove cannot be effectively removed in the subsequent chemical mechanical polishing process, the residue will act as a hard-mask and cannot be effectively completed. Silicon epitaxial chemical mechanical planarization, such as Figure 12 As shown in (A) (due to the large aspect ratio, the slurry will remain in the groove formed after the selective epitaxial filling, and act as a barrier layer to prevent the epitaxial layer from being effectively removed)

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