Folding gate-controlled L-shaped channel tunneling transistor low in leakage current

Abstract

The invention relates to a folding gate-controlled L-shaped channel tunneling transistor low in leakage current. By the adoption of the structural design of a folding gate electrode, the horizontal part and the vertical part of L-shaped intrinsic silicon can be controlled at the same time. By the adoption of the structural design of the L-shaped intrinsic silicon, a device has the higher current rise rate in a subthreshold region and the higher forward break-over capacity, and the band bending near a drain area generated when the device is in the reverse bias state is greatly retarded. Thus, compared with a common tunneling transistor, it is guaranteed that the device has better forward characteristics, lower reverse leakage current and lower static power consumption. The invention further relates to a specific manufacturing method of a device structure unit. The folding gate-controlled L-shaped channel tunneling transistor low in leakage current and the specific manufacturing method of the device structure unit are suitable for application and popularization.

Description

technical field [0001] The invention relates to the field of ultra-large-scale integrated circuit manufacturing, and relates to a specific structural unit and a manufacturing method of a folded gate-controlled L-shaped channel low-leakage current tunneling transistor suitable for ultra-high-integrated integrated circuit manufacturing. Background technique [0002] Currently, silicon-based PIN-type tunneling field-effect transistors (referred to as tunneling transistors) have the potential to achieve better switching characteristics and lower power consumption compared with traditional metal-oxide-semiconductor field-effect transistors (MOSFETs). , so it can replace MOSFETs and become one of the basic unit candidates of the new generation of integrated circuits. The disadvantage of the current tunneling transistor manufactured according to the existing technology is that the gate electrode voltage can generate a considerable tunneling current when it is forward-biased and re...

AI Technical Summary

Problems solved by technology

The disadvantage of the current tunneling transistor manufactured according to the existing technology is that the gate electrode voltage can generate a considerable tunneling current when it is forward-biased and reverse-biased, which makes the static power consumption of the tunneling transistor larger. At the same time, Tunneling transistors manufactured by existing planar technology are similar to MOSFETs. When the channel length of the device is too short, the subthreshold characteristics decrease due to the weakening of the gate electrode control ability and the channel voltage caused by the drain voltage. Dow barrier lowering effect (DIBL) and other issues

[0003] Increasing the dielectric constant of the gate insulating layer can enhance the control ability of the gate electrode to short-channel TFETs devices, improve subthreshold characteristics and solve problems such as DIBL. The problem of generating a large tunneling current, so instead of reducing but increasing the static power consumption of the tunneling transistor

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