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Planar VDMOS device and manufacturing method thereof

A planar, device technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems affecting the dynamic characteristics of power devices, affecting VDMOS parameters, etc., to reduce parasitic capacitance, reduce effective area, reduce The effect of small conduction losses

Inactive Publication Date: 2016-02-17
PEKING UNIV FOUNDER GRP CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0014] In conventional power devices, there is gate-drain capacitance, which will affect the dynamic characteristics of power devices
In order to reduce the gate-to-drain capacitance, there is currently a main method to increase the thickness of the gate oxide layer as a whole, but this will affect other parameters of VDMOS, such as threshold voltage

Method used

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  • Planar VDMOS device and manufacturing method thereof
  • Planar VDMOS device and manufacturing method thereof
  • Planar VDMOS device and manufacturing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0054] image 3 The process flow of a method for manufacturing a planar VDMOS device disclosed in the present invention specifically includes the following steps:

[0055] Step 101, forming a gate oxide layer on the epitaxial layer, and forming a polysilicon layer on the gate oxide layer;

[0056] Step 102, etching the polysilicon layer to form a polysilicon gate;

[0057] Step 103, performing ion implantation to form a doped polysilicon gate;

[0058] Step 104, forming a photoresist mask on the surface of the doped polysilicon gate;

[0059] Step 105, etching a polysilicon gate trench on the doped polysilicon gate;

[0060] Step 106 , performing thermal oxidation on the polysilicon gate trench and the surface of the doped polysilicon gate to form an oxide layer.

[0061] Preferably, a layer of photoresist is coated on the doped polysilicon gate and the gate oxide layer, and then the photoresist is exposed through a mask plate to form a photoresist mask, and dry etching is...

Embodiment 2

[0067] This embodiment provides a method for manufacturing a planar VDMOS device, and its specific process is as follows Figure 4 Shown:

[0068] In step 201, an epitaxial layer of the first conductivity type is formed on the upper surface of the substrate of the first conductivity type.

[0069] In this embodiment, a substrate of the first conductivity type can be provided first, and an epitaxial layer of the first conductivity type is formed on the substrate of the first conductivity type. The substrate of the first conductivity type can be an N-type substrate or a P-type substrate. substrate, when the substrate of the first conductivity type is an N-type substrate, the first conductive epitaxial layer disposed on the N-type substrate is an N-type epitaxial layer; when the substrate of the first conductivity type is a P-type When the substrate is used, the first conductive epitaxial layer disposed on the P-type substrate is a P-type epitaxial layer.

[0070] In step 202, ...

Embodiment 3

[0101] The present invention also provides a planar VDOMS device, at least comprising the following structures:

[0102] A gate structure consisting of a gate oxide layer and a doped polysilicon gate;

[0103] The oxide layer in the gate structure divides the doped polysilicon gate into multiple parts;

[0104] The bottom of the polysilicon gate trench is in contact with the surface of the gate oxide layer.

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Abstract

The invention discloses a planar vertical double-diffusion metal-oxide-semiconductor (VDMOS) device and a manufacturing method thereof. The method comprises: a gate oxide layer is generated on an epitaxial layer and polysilicon layers are generated on the gate oxide layer; the polysilicon layers are etched to form polysilicon gates; ion implantation is carried out to form doped polysilicon gates; photoresist masks are formed on the surfaces of the doped polysilicon gates and the gate oxide layer; the doped polysilicon gates are etched to form polysilicon gate grooves; and thermal oxidation is carried out on the polysilicon gate grooves and the doped polysilicon gate surfaces to form oxide layers. According to the invention, with the change of the structure of the polysilicon gate, the doped polysilicon gates are divided into two parts by the oxide layers, so that the gate-drain capacitance is reduced under the circumstance that no other parameters are affected.

Description

technical field [0001] The invention relates to the technical field of semiconductor chip manufacturing technology, in particular to a planar VDMOS device and a manufacturing method thereof. Background technique [0002] The drain and source poles of the conventional planar VDMOS (vertical double-diffusion metal-oxide-semiconductor, vertical double-diffusion metal-oxide-semiconductor transistor) device are on both sides of the device, so that the current flows vertically inside the device, increasing the current density and improving the rating. The on-resistance per unit area is also small, and it is a power device with a wide range of uses. [0003] The manufacturing process of conventional planar VDMOS devices is as follows: [0004] In step 1, an epitaxial layer 2 is formed on the substrate 1, a gate oxide layer 3 is formed on the epitaxial layer, and a polysilicon layer 4 is formed on the gate oxide layer 3, such as Figure 1a shown. [0005] Step 2, forming a photore...

Claims

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Application Information

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IPC IPC(8): H01L21/336H01L29/78H01L29/423
Inventor 李理马万里赵圣哲
Owner PEKING UNIV FOUNDER GRP CO LTD
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