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Method of forming semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve the problems of etching damage, low overall performance of semiconductor devices, and the second metal gate is easily corroded, so as to avoid corrosion and prevent corrosion

Active Publication Date: 2018-11-16
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The problem solved by the present invention is that in the prior art, when the second metal gate is formed first and then the first metal gate is formed, the second metal gate formed first is easily corroded or damaged by etching, resulting in low overall performance of the semiconductor device

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  • Method of forming semiconductor device

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Embodiment Construction

[0033] It can be seen from the background art that the electrical performance of semiconductor devices formed in the prior art needs to be improved.

[0034]It has been found through research that in order to meet the requirements of improving the threshold voltage (Threshold Voltage) of NMOS tubes and PMOS tubes at the same time, different metal materials are usually used as the work function (WF, WorkFunction) layer materials of the metal gates of NMOS tubes and PMOS tubes, so The metal gates of the NMOS transistor and the PMOS transistor are formed successively, instead of forming the metal gates of the NMOS transistor and the PMOS transistor at the same time.

[0035] In one embodiment, refer to figure 1 , providing a substrate 100, the substrate 100 includes a PMOS region, an NMOS region and other device regions; a first dummy gate 111 is formed on the substrate 100 in the NMOS region, and a second dummy gate 121 is formed on the substrate 100 in the PMOS region, An int...

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Abstract

The invention relates to a formation method of a semiconductor device. The formation method comprises the steps of providing a substrate which comprises a first region, a second region and a third region, wherein the substrate in the first region is provided with a first pseudo gate, the substrate in the second region is provided with a second metal gate, and the surface of the substrate in the first region and the second region is provided with an interlayer dielectric layer, converting partial thickness of the second metal gate into a nitrided metal protection layer, forming an initial gallium nitride layer on the substrate in the third region, the surface of the first pseudo gate, the surface of the nitrided metal protection layer and the surface of the interlayer dielectric layer, etching the initial gallium nitride layer by adopting a dry etching process so as to form a gallium nitride layer located at the substrate in the third region, etching the first pseudo gate by taking the gallium nitride layer as a mask so as to form a first opening in the interlayer dielectric layer in the first region, and forming a first metal gate which fully fills the first opening. During the process of forming the semiconductor device, the second metal gate always protected by the nitrided metal protection layer, so that the formed semiconductor device is good in electrical performance.

Description

technical field [0001] The invention relates to the technology in the field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] At present, in the manufacturing process of semiconductor devices, a P-type metal oxide semiconductor (PMOS, P type Metal Oxide Semiconductor) tube, an N-type metal oxide semiconductor (NMOS, N type Metal Oxide Semiconductor) tube, or a combination of a PMOS tube and an NMOS tube The formed Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) tube is the main device constituting the chip. [0003] With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of devices are continuously reduced following Moore's law. When the device size is reduced to a certain extent, various secondary effects caused by the physical limit of t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28H01L21/8238
Inventor 张海洋张城龙
Owner SEMICON MFG INT (SHANGHAI) CORP
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