Method of manufacturing bonding structure for multi-layer bonding stack and bonding structure

Abstract

The invention relates, in particular, to a method of manufacturing a bonding structure for a multi-layer bonding stack and a bonding structure. The method includes the steps of depositing front bonding points at preset positions on a surface of a dielectric layer of a wafer, the wafer including a first substrate and the dielectric layer, and the dielectric layer including a plurality of metal connection points; leading out a part of the metal connection points to form metal transfer points; performing through-hole etching at the metal transfer points to form a plurality of through-holes; performing conductive metal deposition on the inside of the through-holes to fill the through-holes; and subjecting a far surface of the substrate away from the dielectric layer to thinning and chemical mechanical planarization processing until the conductive metal is exposed, and forming, by taking the conductive metal as backside bonding points, the bonding structure for the multi-layer bonding stack and with bonding points on both the front and back sides. The bonding stack of a plurality of wafers or chips can be realized by the method of the invention, the freedom of the circuit design of an integrated circuit chip and the effective utilization area of the chip can be effectively improved, and the problems such as high resistance caused by too long connection wires and bandwidth decrease are reduced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a bonding structure manufacturing method and bonding structure for multilayer bonding stacking. Background technique [0002] As electronic products, especially portable products such as mobile phones become smaller and smaller, but at the same time must be able to provide more and more functions, so it is necessary to integrate multiple functional chips, electronic components such as semiconductor devices are a multi- Made of laminated structure. [0003] To electrically connect components in different layers, through-silicon via (TSV) technology can be used to provide electrical interconnection and provide mechanical support. In through-silicon via technology, holes are drilled in specific areas of each silicon wafer and filled with metal. Finally, each perforated silicon wafer is stacked and bonded together and cut into individual chips. This wil...

AI Technical Summary

Problems solved by technology

Finally, each perforated silicon wafer is stacked and bonded together and cut into individual chips. This will not only lose the effective area of ​​each chip, but also increase the resistance of the chip and reduce the bandwidth because the interconnection line is too long. And other problems, more importantly, the freedom of circuit design is severely limited due to the fact that the location of the interconnection vias can only be located in a specific area of ​​the silicon wafer.

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