Low temperature epitaxial method and apparatus

Abstract

The invention provides a low temperature epitaxial method and apparatus. The method includes the steps of S1 providing a substrate including a substrate and at least one semiconductor fin protruding out of the substrate surface, S2, growing an epitaxial layer on the sidewall and the upper surface of the semiconductor fin in an epitaxial way, and S3 etching the epitaxial layer by using cracked etching gas subjected to ultraviolet irradiation to reduce the thickness of the epitaxial layer. The thickness of an epitaxial layer is reduced by etching in an epitaxial growth process, to improve the surface contour of the surface epitaxial layer of the semiconductor fin, thereby preventing fusion between adjacent surface epitaxial layers of the semiconductor fin, or minimizing the gap generated after fusion of the epitaxial layers. The etching rate of the etching gas on the epitaxial layer can be improved, the process temperature during reducing of the etching of the epitaxial layers can be reduced, a process window is expanded, and the process difficulty is reduced.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and relates to a low-temperature epitaxy method and device. Background technique [0002] As the size of integrated circuits becomes smaller and the requirements for integrated circuits gradually increase, transistors need to have higher drive currents with smaller and smaller sizes, so fin field-effect transistors (Fin field- effect transistors; FinFETs). [0003] Similar to planar transistors, source and drain silicides may be formed on the source and drain regions of the FinFET. However, since the fins of the FinFET are usually very narrow, current crowding occurs. In addition, it is difficult to place a contact plug on the source / drain of the fin, so an epitaxial semiconductor layer is formed on the fin by using an epitaxial process to increase the volume of the fin. [0004] However, the epitaxy process has some disadvantages. figure 1 A cross-sectional view of a semiconductor ...

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Problems solved by technology

[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a low-temperature epitaxy method and device, which is used to solve the problem in the prior art that the epitaxial layers on the surface of adjacent semiconductor fins are easy to fuse and there is a large fusion gap. question

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