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Si-based vertical cavity surface emitting chip

A vertical cavity surface emission and chip technology, which is applied in the direction of phonon exciters, laser components, electrical components, etc., can solve the problems of not being able to emit light directly, and it is difficult to realize continuous operation of silicon-based VCSLE at room temperature, so as to facilitate mass production , The effect of preparation process compatibility

Active Publication Date: 2018-03-02
张子旸
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Problems solved by technology

Silicon-based light sources have always been a hot spot of concern due to their ease of integration, low cost, low energy consumption, and mature technology. However, Si, as an indirect bandgap semiconductor, cannot directly emit light, and it is difficult to achieve epitaxial growth of GaAs on silicon as an active layer. Room temperature continuous operation of silicon-based VCSLE

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  • Si-based vertical cavity surface emitting chip
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  • Si-based vertical cavity surface emitting chip

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preparation example Construction

[0035] The preparation method of Si-based vertical cavity surface emission chip, the specific steps are as follows:

[0036](1) Clean the Si substrate 20 and treat the oxide layer on the surface of the substrate 20 with hydrofluoric acid, and use pulsed laser deposition or magnetron sputtering to epitaxially grow Ga on the treated substrate 20 2 O 3 buffer layer 30;

[0037] (2) Alternately growing Al-doped gallium oxide mixtures with different doping concentrations on the buffer layer 30 as the lower distributed Bragg mirror 40;

[0038] (3) Epitaxial growth of rare earth doped Ga on the lower distributed Bragg mirror 40 2 O 3 as the active layer 50;

[0039] (4) Two kinds of dielectric materials are alternately grown on the active layer 50 as the upper distributed Bragg mirror 60;

[0040] (5) The epitaxial structure composed of the buffer layer 30, the lower distributed Bragg mirror 40, the active layer 50, and the upper distributed Bragg mirror 60, such as figure 1 A...

Embodiment 1

[0047] This embodiment provides a silicon-based vertical cavity surface emitting light source, such as image 3 As shown, the silicon-based vertical cavity surface emitting light source structure includes an n-type electrode 10, a substrate 20, a buffer layer 30, a lower distributed Bragg mirror 40, an active layer 50, an upper distributed Bragg mirror 60, and a p-type electrode 70 , confinement layer 80 , light exit window 90 .

[0048] In this embodiment, the substrate 20 is an n-type silicon wafer, which provides support for the entire light source structure. The epitaxial growth buffer layer 30 is deposited on the substrate by using pulsed laser, and the buffer layer material is Ga 2 O 3 , with a thickness of 500 nm, providing a transition for growing distributed Bragg mirrors 40 with high quality. The lower distributed Bragg mirror 40 is then grown on the buffer layer, and the lower distributed Bragg mirror 40 is composed of a periodically grown dielectric material 401...

Embodiment 2

[0052] This embodiment provides a silicon-based vertical cavity surface emitting light source, such as image 3 As shown, the silicon-based vertical cavity surface emitting light source structure includes an n-type electrode 10, a substrate 20, a buffer layer 30, a lower distributed Bragg mirror 40, an active layer 50, an upper distributed Bragg mirror 60, and a p-type electrode 70 , confinement layer 80 , light exit window 90 .

[0053] In this embodiment, the substrate 20 is an n-type silicon wafer, which provides support for the entire light source structure. The epitaxial growth buffer layer 30 is deposited on the substrate by using pulsed laser, and the buffer layer material is Ga 2 O 3 , with a thickness of 500 nm, providing a transition for growing distributed Bragg mirrors 40 with high quality. The lower distributed Bragg mirror 40 is then grown on the buffer layer, and the lower distributed Bragg mirror 40 is composed of a periodically grown dielectric material 401...

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Abstract

The invention discloses a Si-based vertical cavity surface emitting chip. The structure consists from bottom to top of an n-type electrode, a substrate, a buffer layer, a lower distributed Bragg reflector located on the substrate, active area located on the lower distributed Bragg reflector, an upper distributed Bragg reflector located on the active area, a p-type electrode located on the upper distributed Bragg reflector, and a SiO2 confinement layer located around a cylindrical mesa. In the invention, a silicon-doped (AlxGa1-x)2O3, (AlyGa1-y)2O3 stacked structure is prepared on an n-type silicon substrate as the lower distributed Bragg reflector, rare earth-doped Ga2O3 is used as an n-type luminous material, and a GaAs, AlGaAs or InP, InGaAsP stacked structure is used as the upper distributed Bragg reflector. As a silicon-based vertical cavity surface emitting light source according to the invention, the characteristics of high thermal stability, high chemical stability, simple preparation method and high reliability are gained.

Description

technical field [0001] The invention relates to a Si-based vertical cavity surface emission chip, and belongs to the technical field of semiconductor electronics. Background technique [0002] In recent years, due to the continuous development of the Internet and the continuous improvement of optical storage density, vertical cavity surface emitting light sources, which are the core devices of optical communication and optical storage, have become the focus of researchers' attention. The concept of Vertical Cavity Surface Emitting Laser (VCSLE) was proposed in 1977 by Kenich Iga of Tokyo Institute of Technology, Japan. After years of development, it has made great progress. Especially in recent years, with the widespread popularity of smart phones, people have higher and higher requirements for high-speed wireless communication, which greatly promotes the development of vertical cavity surface emitting light sources. In addition to traditional applications, people have expa...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01S5/187H01S5/323
CPCH01S5/187H01S5/323
Inventor 张子旸王旭王美芳刘永刚
Owner 张子旸
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