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41results about How to "Reduce the difficulty of growing" patented technology

High-mobility quantum-dot field effect transistor and manufacturing method thereof

The invention discloses a high-mobility quantum-dot field effect transistor which comprises a substrate, a first stress buffer layer, a second stress buffer layer, a doping layer, a spacer layer, a channel layer, a lower potential barrier layer, a quantum-dot layer, an upper potential barrier layer, two cap layers, a first electrode, a second electrode and a third electrode, wherein the first stress buffer layer is manufactured on the substrate; the second stress buffer layer is manufactured on the first stress buffer layer; the doping layer is manufactured on the second stress buffer layer; the spacer layer is manufactured on the doping layer; the channel layer is manufactured on the spacer layer; the lower potential barrier layer is manufactured on the channel layer; the quantum-dot layer is manufactured on the lower potential barrier layer; the upper potential barrier layer is manufactured on the quantum-dot layer, a concave mesa is arranged on the middle of the top of the upper potential barrier layer, one side of the concave mesa is provided with a source region, and the other side of the concave mesa is provided with a drain region; the two cap layers are respectively manufactured on the source region and the drain region which are at the two sides of the upper potential barrier layer; the first electrode is manufactured on the top of one cap layer; the second electrode is manufactured on the top of the other cap layer; and the third electrode is manufactured on the concave mesa on the top of the upper potential barrier layer.
Owner:INST OF SEMICONDUCTORS - CHINESE ACAD OF SCI

Long-wave infrared space modulation interference miniaturizing method

The invention relates to a long-wave infrared space modulation interference miniaturizing method. The method is characterized in that an interference assembly is composed of a spectroscope, a pyramid reflector I, a pyramid reflector II and two aperture diaphragms; an included angle between the spectroscope and parallel incident light is 135degree; from the optical axis position of reflected light, the top position of the pyramid reflector I starts to move anticlockwise for 1 / 4 transverse shear amount along the direction vertical to the optical axis of the reflected light; from the optical axis position of transmitted light, the top position of the pyramid reflector II starts to move anticlockwise for 1 / 4 transverse shear amount along the direction vertical to the optical axis of the transmitted light; and the two aperture diaphragms are respectively arranged at the top positions of the two pyramid reflectors, and are respectively placed vertical to the optical axes of the reflected light and the transmitted light. Under the condition that optical parameters are consistent, the size of the spectroscope is decreased, the sizes of the interference assembly and a spectrometer are effectively controlled, the difficulties in material growing and processing are reduced, and the cost is saved.
Owner:KUNMING INST OF PHYSICS

Preparation method of rare earth substituted yttrium iron garnet crystal

InactiveCN110904506APromotes growth and growthReduce growing difficulty and energy costPolycrystalline material growthAfter-treatment detailsYttrium iron garnetBoule
The invention discloses a preparation method of a rare earth substituted yttrium iron garnet crystal. The method includes the steps of: respectively weighing Y2O3, Re2O3 and Fe2O3 in molar ratio according to Y(3-x)RexFe5O12, conducting grinding and briquetting, and then carrying out solid-phase reaction to obtain a polycrystalline material block; crushing and grinding the polycrystalline materialblock, and adding a fluxing agent to obtain a mixed material; putting the mixed material into a crucible, putting the crucible into a crystal growth furnace, performing heating to a set temperature, and conducting heat preservation to obtain a high-temperature solution; then changing the relative positions of the crucible and a heating coil to enable the crucible to gradually move to a low-temperature area until the high-temperature solution is completely crystallized, stopping moving, and performing cooling to room temperature to obtain a crystal ingot; and removing the fluxing agent by adopting mechanical stripping or solution corrosion method to obtain the crystal. By means of the fluxing agent, the method provided by the invention effectively lowers the crystal growth temperature and reduces energy consumption, provides a driving force for crystal growth through vertical movement, promotes the growth of crystals, and can acquire the large-size blocky crystal.
Owner:SHANGHAI APPLIED TECHNOLOGIES COLLEGE

Transmissive AlGaN ultraviolet photocathode preparation method based on substrate stripping

The invention relates to a method for preparing a transmissive AlGaN ultraviolet photocathode based on substrate peeling, comprising the following steps: 1) preparing a material; 2) sequentially carryout high-temperature baking, nucleate layer growth and high-quality GaN release layer growth; 3) growing a p-type Mg doped AlGaN photoemissive layer with high aluminum content; 4) bon that quartz window material on the surface of the AlGaN; 5) that GaN lay is thoroughly decomposed by use a laser decomposition technology, and the substrate is stripped; 6) activating surface of the AlGaN by Cs or Cs/O layer. 1) GaNis taken as that buffer lay of the ultraviolet photoelectric cathode instead of AlN, so that the growth difficulty of the buffer layer is reduce, the crystal quality of the p-type AlGaN emitting layer is improved, and the photocathode with higher sensitivity is prepared; 2) that lase decomposition technology of the buffer lay is adopted to fully decompose the GaN layer and realizethe substrate peeling off, thereby avoiding the absorption of the ultraviolet incident light by the substrate and the buff layer and ensuring the efficient detection of the ultraviolet light by the photoemission layer; 3) the substrate peeled off by the laser can be used repeatedly and economically.
Owner:NO 55 INST CHINA ELECTRONIC SCI & TECHNOLOGYGROUP CO LTD

Method for growing yttrium iron garnet crystals by adopting composite fluxing agent

The invention discloses a method for growing yttrium iron garnet crystals by adopting a composite fluxing agent. The yttrium iron garnet (Y3Fe5O12, YIG for short) crystal is an important magneto-optical material and is prepared by the following steps: accurately weighing, mixing, grinding and sintering raw materials to obtain a polycrystal material, crushing the polycrystal material, adding the composite fluxing agent, carrying out ball milling to obtain a mixed material, filling a crucible with the mixed material, heating the crucible filled with the material to a set temperature, keeping thematerial at the temperature to obtain high-temperature molten crystal solution, then carrying out slow cooling until the solution in the crucible is completely cooled and crystallized, conducting cooling to room temperature to obtain a crystal ingot, and removing the fluxing agent by adopting a mechanical stripping and chemical corrosion method to finally obtain the crystal. According to the invention, through the lead-free composite fluxing agent, environmental pollution caused by lead and the corrosion to a platinum crucible are greatly reduced, the growth temperature of the crystal is effectively reduced, and the bulk single crystal with a larger size can be obtained.
Owner:SHANGHAI INST OF TECH

Method for preparing large size lithium tetraborate piezoelectric crystal

The invention relates to a preparation method of lithium tetraborate piezoelectric crystal, in particular to a preparation method of large-size lithium tetraborate piezoelectric crystal. The preparation method comprises the following steps: a synthetized lithium tetraborate polycrystal material is pressed into compact cylindrical blocks; the blocks are put into a Pt crucible in which seed crystal is put in earlier and into an oven; the oven temperature is controlled to be 950 DEG C to 1000 DEG C, the descending speed of the crucible is 0.1mm / h to 0.6mm / h, and high-grade large monocrystal with thickness of 30mm to 80mm, width more than 120mm and length more than 150mm can be grown; the large monocrystal is processed in the side direction, i.e. the direct along the side with larger size serves as the axial direction of a crystal bar and the side with smaller size serves as the thickness direction of the crystal bar, and a large-size lithium tetraborate piezoelectric crystal profile is obtained. Compared with traditional descending methods, the method solves the technical bottlenecks of difficulty in inoculation, easily leaking crucible, easy cracking of the crystal and the like in the growth of large-size lithium tetraborate piezoelectric crystal through traditional descending methods, adopts sideward growth and flat crucible design, can improve the growth speed of the crystal, thereby reducing the growth difficulty of the crystal and helping to realize the industrialized growth of the large-size lithium tetraborate piezoelectric crystal.
Owner:SHANGHAI INST OF TECH

Method for improving reliability of gate oxide layer of peripheral circuit area of flash memory

The invention provides a method for improving the reliability of a gate oxide layer of a peripheral circuit area of a flash memory. The method includes the following steps that: oxidation treatment is performed on a nitrogen containing region of the top of a semiconductor substrate at the peripheral circuit area; and the nitrogen containing region is converted into an oxide layer, and the oxide layer is removed, and therefore, a nitrogen-free semiconductor substrate surface of the peripheral circuit area is exposed; and a gate oxide layer is grown on the nitrogen-free semiconductor substrate surface. With the method adopted, when an MOS device is manufactured in the peripheral circuit area in a subsequent process, the nitrogen containing region of the top of the semiconductor substrate is removed, and therefore, the growth difficulty of the gate oxide layer on the surface of the semiconductor substrate can be lowered, and especially, the growth capacity of the gate oxide layer on the semiconductor substrate at corners of an isolation structure can be improved, and the integrity and uniformity of gate oxide layer growth can be increased, and the reliability of the gate oxide layer of the MOS device can be improved; and the oxidation treatment mentioned in the invention is performed at room temperature or low temperature, and therefore, thermal budget in the prior art can be decreased, and device doping profile shift can be avoided. The method is advantageous in convenient implementation and simple operation.
Owner:SEMICON MFG INT (SHANGHAI) CORP

Type-II superlattice structure based on indium arsenide and preparation method

The invention discloses a type-II superlattice structure based on indium arsenide and a preparation method. The type-II superlattice structure based on indium arsenide comprises an InAs layer, a GaAs layer, a GaAsxSb1-xlayer and a GaAs layer from bottom to top, and is characterized in that: (1) an original GaSb substrate is replaced with an InAs substrate, so that the growth temperature of superlattices is substantially increased, and the increasement of the growth temperature is conductive to increasing a diffusion length of surface atoms, thereby being more conductive to the two-dimensional growth of materials and the reduction of material defect density; (2) an As valve is always in an open state during the whole growth process of type-II superlattices, so that a GaAsSb ternary compound is formed due to the outflow of partial As when growing a GaSb layer, growth temperature of the layers tends to be uniform due to the existence of the common element As in the layers, and the counterdiffusion at interfaces is reduced; (3) variation of thickness of the InAs layer has small influence on mismatching of the InAs-based type-II superlattices, the growth difficulty of long waves materials, particularly extremely-long-wave materials, is extremely reduced, and the performance and quality of the materials can be more easily improved.
Owner:SHANGHAI INST OF TECHNICAL PHYSICS - CHINESE ACAD OF SCI

Multi-wavelength semiconductor laser based on annular resonant cavity

The invention discloses a multi-wavelength semiconductor laser based on an annular resonant cavity and belongs to the field of semiconductor lasers. The multi-wavelength semiconductor laser comprises a substrate layer, a buffer layer, a lower cladding, an active layer, an upper cladding and an ohmic contact layer which are arranged from bottom to top, wherein the laser is provided with more than one annular ridge waveguide and a coupled waveguide, each annular ridge waveguide is formed by at least the ohmic contact layer and part of the upper cladding or the whole upper cladding and can generate laser beams under forward bias, and the coupled waveguide can amplify the optical power of the laser beams under forward bias; the annular ridge waveguide and the active layer form the annular resonant cavity; the circumferences of the annular ridge waveguides are not equal; and the coupled waveguide is arranged adjacent to the annular ridge waveguides. The multi-wavelength semiconductor laser based on the annular resonant cavity has the advantages that the multi-wavelength semiconductor laser is simple and compact in structure and is easy in integration with other devices; the process is simplified, and the cost is lowered; the superposition of active layers of a plurality of single longitudinal-mode lasers is avoided, and the difficulty in the growth of materials is reduced; and the output paths of the laser beams are flexible and adjustable, and the large-scale integration of lasers is easily implemented.
Owner:THE 13TH RES INST OF CHINA ELECTRONICS TECH GRP CORP

Semiconductor epitaxial structure, vcsel and manufacturing method based on flexible substrate

The invention provides a semiconductor epitaxial structure, VCSEL and manufacturing method based on a flexible substrate. Fluorphlogopite mica is used as the substrate, which not only solves the problem that the existing semiconductor substrate cannot be bent and is not easy to peel off, but also takes into account the cost of the semiconductor device. temperature requirements. For the buffer layer, the multi-layer first GaInP buffer layer is gradually changed layer by layer, showing a step gradient trend. By inserting the second layer of the In composition gradient opposite to the direction of the In composition gradient between two adjacent first GaInP buffer layers. The GaInP buffer layer forms a structure with fluctuating and gradual changes in the In composition, thereby introducing compressive stress in the buffer layer, increasing the interaction of dislocations, making the surface smoother, and further reducing threading dislocations, improving the performance of fluorine phlogopite. The quality of the epitaxial layer on the substrate realizes the application of fluorophlogopite substrate in semiconductor devices. VCSEL has the advantages of being bendable, easy to peel off, good epitaxial layer quality, and high light extraction efficiency.
Owner:XIAMEN QIANZHAO SEMICON TECH CO LTD

Miniaturization method of long-wave infrared spatial modulation interferometry

The invention relates to a long-wave infrared space modulation interference miniaturizing method. The method is characterized in that an interference assembly is composed of a spectroscope, a pyramid reflector I, a pyramid reflector II and two aperture diaphragms; an included angle between the spectroscope and parallel incident light is 135degree; from the optical axis position of reflected light, the top position of the pyramid reflector I starts to move anticlockwise for 1 / 4 transverse shear amount along the direction vertical to the optical axis of the reflected light; from the optical axis position of transmitted light, the top position of the pyramid reflector II starts to move anticlockwise for 1 / 4 transverse shear amount along the direction vertical to the optical axis of the transmitted light; and the two aperture diaphragms are respectively arranged at the top positions of the two pyramid reflectors, and are respectively placed vertical to the optical axes of the reflected light and the transmitted light. Under the condition that optical parameters are consistent, the size of the spectroscope is decreased, the sizes of the interference assembly and a spectrometer are effectively controlled, the difficulties in material growing and processing are reduced, and the cost is saved.
Owner:KUNMING INST OF PHYSICS

High-strain semiconductor structure and preparation method thereof

The invention provides a high-strain semiconductor structure and a preparation method thereof, and in a composite active layer of the high-strain semiconductor structure, the indium content in a first component gradient layer is smaller than the indium content in a quantum well layer and larger than the indium content in a first barrier layer. The indium content in the second component gradient layer is smaller than the indium content in the quantum well layer and larger than the indium content in the second barrier layer; the indium component content in a plurality of first sub-gradient layers in the first component gradient layer meets a progressive increase area of a Gaussian function along with the increase of the number of the first sub-gradient layers, and the indium component content in a plurality of second sub-gradient layers in the second component gradient layer meets a progressive decrease area of the Gaussian function along with the increase of the number of the second sub-gradient layers; the content of indium in the first stress compensation layer and the second stress compensation layer is zero; and the quantum well layer, the first component gradient layer and the second component gradient layer are used for laser light. The process difficulty and complexity of the high-strain semiconductor structure are reduced, and the growth quality is improved.
Owner:SUZHOU EVERBRIGHT PHOTONICS CO LTD +1

A method for improving the reliability of gate oxide layer in peripheral circuit region of flash memory

ActiveCN104112656BAvoid shifting doping profilesAvoid offsetSemiconductor devicesState of artRoom temperature
The invention provides a method for improving the reliability of a gate oxide layer of a peripheral circuit area of a flash memory. The method includes the following steps that: oxidation treatment is performed on a nitrogen containing region of the top of a semiconductor substrate at the peripheral circuit area; and the nitrogen containing region is converted into an oxide layer, and the oxide layer is removed, and therefore, a nitrogen-free semiconductor substrate surface of the peripheral circuit area is exposed; and a gate oxide layer is grown on the nitrogen-free semiconductor substrate surface. With the method adopted, when an MOS device is manufactured in the peripheral circuit area in a subsequent process, the nitrogen containing region of the top of the semiconductor substrate is removed, and therefore, the growth difficulty of the gate oxide layer on the surface of the semiconductor substrate can be lowered, and especially, the growth capacity of the gate oxide layer on the semiconductor substrate at corners of an isolation structure can be improved, and the integrity and uniformity of gate oxide layer growth can be increased, and the reliability of the gate oxide layer of the MOS device can be improved; and the oxidation treatment mentioned in the invention is performed at room temperature or low temperature, and therefore, thermal budget in the prior art can be decreased, and device doping profile shift can be avoided. The method is advantageous in convenient implementation and simple operation.
Owner:SEMICON MFG INT (SHANGHAI) CORP
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