Preparation method of shallow trench isolation structure

Abstract

The invention relates to a preparation method of a shallow trench isolating structure. The preparation method comprises the following steps: successively depositing on the surface of a silicon substrate wafer to form a silicon oxide layer and a silicon nitride layer, and carrying out photoetching on the surface to form a trench which penetrates through the silicon oxide layer and the silicon nitride layer and extends into a silicon substrate; depositing silicon oxide in the trench and enabling the trench to be filled with silicon oxide; grinding by using chemical machinery to remove redundantsilicon oxide on the surface of the silicon nitride layer to form a flat-surface trench silicon oxide filling structure; pre-cleaning the trench silicon oxide filling structure by using a concentratedsulfuric acid and hydrogen peroxide mixed solution; regularly cleaning the trench silicon oxide filling structure; and removing the silicon nitride layer to form the shallow trench isolating structure. By the preparation method of the shallow trench isolating structure, the defect amount of a chip can be reduced, the yield of a trench silicon oxide filling structure product is improved, and the economic benefit is quite high.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing technology, in particular to a preparation method of a shallow trench isolation structure. Background technique [0002] In recent years, in order to eliminate the mutual influence between semiconductor elements, shallow trench isolation (STI) with a small element isolation width has been introduced in semiconductor manufacturing. The STI method is to etch a groove in the silicon substrate layer, and then fill the groove with a silicon oxide insulating layer to form an electrically insulating component area. The STI method flow is as follows: first, silicon oxide and silicon nitride layers are respectively formed on the silicon substrate, then grooves are formed on the surface of the wafer and filled with the silicon oxide layer, and finally the excess oxide on the silicon nitride layer is removed by chemical mechanical polishing (CMP). Silicon layer, and then remove the silicon nitride...

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Problems solved by technology

Among them, after CMP, it must be cleaned to remove particles, so as not to form a large number of defects after removing silicon nitride, which will affect the yield of the product.

[0003] The traditional method of depositing a silicon oxide layer is a high-density plasma process (HDP), but with the increasing demand for high integration and high performance of VLSI, semiconductor technology is developing towards a technology node with a feature size of 65nm or even smaller. The width of the gap is correspondingly reduced, and the depth ratio is also increased, which requires further improvement of the gap-filling ability of thin film deposition. High Aspect Ratio Process (HARP) instead

[0004] However, although the high aspect ratio process has better gap filling ability, the quality of the deposited silicon oxide is relatively poor, resulting in high internal stress, loose silicon oxide film and sometimes even cracks, so a large number of cracks are prone to appear during the chemical mechanical polishing process. Silicon oxide particles, and the surface of these silicon oxide particles is coated with organic matter in the chemical mechanical polishing liquid, which is difficult to remove, which will lead to a decrease in the yield of the product

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