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Semiconductor package structure with pin sidewall tin climbing function and its manufacturing process

A technology of packaging structure and manufacturing process, which is applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as delamination, improve soldering performance, improve soldering reliability, and increase bonding area effect

Active Publication Date: 2020-03-06
JCET GROUP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] However, this kind of packaging structure that forms L-shaped outer leads or C-shaped outer leads by cutting ribs also has the following defects when forming L-shaped outer leads or C-shaped outer leads: first, the outer When the pins are formed, the outer pins are bent toward the side of the plastic package, Figure 1G and Figure 1H The inner pin at A will be affected by the rebound force of the metal, which will cause the metal pin to have the stress of being pushed away from the plastic package downwards, and in the case of this downward force, it is easy to cause A. Delamination occurs between the upper surface of the inner pin and the lower surface of the molding compound

Method used

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  • Semiconductor package structure with pin sidewall tin climbing function and its manufacturing process
  • Semiconductor package structure with pin sidewall tin climbing function and its manufacturing process
  • Semiconductor package structure with pin sidewall tin climbing function and its manufacturing process

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Embodiment Construction

[0059] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0060] Such as figure 2 , image 3 As shown, in this embodiment, a semiconductor package structure with the function of climbing tin on the side wall of the pins includes a base island 1 and pins 2, and the base island 1 and pins 2 are metal circuit layers formed by electroplating. The pin 2 is arranged around the base island 1, the pin 2 includes a plane portion 2.1 and a side wall portion 2.3, the side wall portion 2.3 is located outside the plane portion 2.1, and the side wall portion 2.3 includes a plurality of side wall surfaces , the planar part 2.1 and the multiple side wall surfaces of the side wall part 2.3 are transitionally connected by an arc part 2.2, the convex surface of the arc part 2.2 faces the outer lower side, and the front of the base island 1 is connected by a bonding substance or The solder 3 is provided with a chip 4...

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Abstract

The invention relates to a semiconductor package structure having a pin side wall tin climbing function and a manufacturing process thereof. The structure comprises a paddle and pins, wherein each pincomprises a planar part and a side wall part, the side wall part comprises a plurality of side wall surfaces, the planar part and the plurality of side wall surfaces of the side wall part are in transition connection by an arc part, a chip is arranged on a front surface of the paddle by a binding substance or a welding material, a plastic sealing material wraps peripheral regions of the paddle, the pins and the chip, the plurality of side wall surfaces of the side wall part and the arc parts form wavelike protruding parts by coating of the plastic sealing material, and outer surfaces of the planar parts, the arc parts and the side wall parts are exposed out of the plastic sealing material. Welding tin can climb to a relatively high height along the vertical side walls during welding of aPCB, so that the bonding area of the welding tin and the pins is expanded, meanwhile, air at the pins can be discharged along protruding arcs, so that the welding performance and the reliability of aproduct are improved.

Description

technical field [0001] The invention relates to a semiconductor packaging structure with the function of tin climbing on the side wall of a pin and a manufacturing process thereof, belonging to the technical field of semiconductor packaging. Background technique [0002] With the development of modern technology, semiconductor packaging has been widely used. Its extensive applications in radar, remote control telemetry, aerospace, etc. put forward higher and higher requirements for its reliability. The failure caused by poor soldering of semiconductors has attracted more and more attention, because this failure is often fatal and irreversible. Therefore, it is very important to get a good soldering reliability in the semiconductor industry. The tin layer on the soldering surface of the semiconductor can make the soldering stronger, especially for automotive electronics. [0003] As we all know, QFN (Quad Flat No-lead Package, four-sided leadless flat package) and DFN (Duad...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/495H01L23/31H01L21/50H01L21/56
CPCH01L21/50H01L21/56H01L23/3114H01L23/49541H01L2224/48091H01L2224/48247H01L2224/97H01L2924/181H01L2924/00014H01L2924/00012
Inventor 梁志忠刘恺王亚琴
Owner JCET GROUP CO LTD
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