Graphene/silicon heterojunction CCD (charge coupled device) pixel array based on SOI (silicon on insulator) substrate and production method thereof
A silicon heterojunction and pixel array technology, applied in the field of image sensors, can solve problems such as slow response speed, abnormal data transmission, difficulty in controlling CCD yield, etc., to reduce dark current, improve system response speed, and improve ultraviolet light The effect of response
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Embodiment 1
[0030] Depend on figure 1 As shown, a kind of graphene / silicon heterojunction CCD pixel array based on the SOI substrate of the present embodiment includes several pixels forming the array, and the pixels successively include gate 7, SOI substrate substrate 6, The oxide insulating layer 5, the source electrode 1, the top layer silicon 3 of the SOI substrate, the graphene film 2 and the drain electrode 4; the source electrode 1 and the drain electrode 4 are horizontally arranged on the upper surface of the oxide insulating layer 5; the graphene film 2 is overlapped with the top layer of silicon 3 of the SOI substrate and is placed on the upper surface of the oxide insulating layer 3 between the source 1 and the drain 4, and the graphene film 2 covers the top of the source 1, and the top layer of the SOI substrate The silicon 3 is disposed under the drain 4 .
[0031] The SOI substrate substrate 6 is p-type lightly doped silicon with a resistivity of 1-10Ω·cm;
[0032] The top...
Embodiment 2
[0040] Depend on figure 1 As shown, a kind of graphene / silicon heterojunction CCD pixel array based on the SOI substrate of the present embodiment includes several pixels forming the array, and the pixels successively include gate 7, SOI substrate substrate 6, The oxide insulating layer 5, the source electrode 1, the top layer silicon 3 of the SOI substrate, the graphene film 2 and the drain electrode 4; the source electrode 1 and the drain electrode 4 are horizontally arranged on the upper surface of the oxide insulating layer 5; the graphene film 2 is overlapped with the top layer of silicon 3 of the SOI substrate and is placed on the upper surface of the oxide insulating layer 3 between the source 1 and the drain 4, and the graphene film 2 covers the top of the source 1, and the top layer of the SOI substrate The silicon 3 is disposed under the drain 4 .
[0041] SOI substrate 6 is n-type lightly doped silicon, and the oxide insulating layer 5 is silicon dioxide;
[0042]...
Embodiment 3
[0050] Depend on image 3 As shown, a kind of graphene / silicon heterojunction CCD pixel array based on the SOI substrate of the present embodiment includes several pixels forming the array, and the pixels successively include gate 7, SOI substrate substrate 6, The oxide insulating layer 5, the source electrode 1, the top layer silicon 3 of the SOI substrate, the graphene film 2 and the drain electrode 4; the source electrode 1 and the drain electrode 4 are horizontally arranged on the upper surface of the oxide insulating layer 5; the graphene film 2 is overlapped with the top layer of silicon 3 of the SOI substrate and is placed on the upper surface of the oxide insulating layer 3 between the source 1 and the drain 4, and the graphene film 2 covers the top of the source 1, and the top layer of the SOI substrate The silicon 3 is disposed under the drain 4, and a buried trench layer 8 is disposed between the SOI substrate 6 and the oxide insulating layer 5;
[0051] The SOI su...
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Abstract
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