Pseudo-gate removal method for fdsoi devices

Abstract

The invention discloses a method for removing a pseudo-gate of an FDSOI device. The silicon nitride sidewall of the device is partially removed through the stress proximity technology, and the interlayer dielectric oxide layer is chemically mechanically ground to stop on the tensile stress silicon nitride film, and the remaining The tensile stress silicon nitride film is the initial layer of plasma etching, and the dummy gate is etched and removed by using the terminal mode. The invention can reduce the damage of phosphoric acid on the source-drain germanium-silicon layer in the existing process and the loss of the silicon nitride hard mask on the top of the pseudo-gate, realize the stress proximity effect and protect the gate shape at the same time, and can effectively ensure the completion of final etching Afterwards, the difference in gate height between different wafers, different batches, and regions of different pattern densities on the same wafer is very small. At the same time, due to the use of the end point mode, silicon nitride will stop in time after etching. The final gate height is controlled by etching the single-step time of the amorphous silicon layer, and the gate height is controllable and the process is easy to control.

Description

technical field [0001] The invention relates to the field of manufacturing microelectronics and semiconductor integrated circuits, in particular to the manufacturing process of gate-last FDSOI (Fully Depleted Silicon On Insulator, fully depleted silicon-on-insulator) integrated circuits, and in particular belongs to a pseudo-type FDSOI device. Gate removal method. Background technique [0002] Planar FDSOI technology is currently the most promising semiconductor manufacturing process route other than FinFET (Fin Field-Effect Transistor) technology route. Its typical feature is that the wafer used has a layer of buried silicon oxide. (Buried oxide, BOX) and a layer of ultra-thin silicon on insulator (silicon oninsulator, namely SOI). Based on the above characteristics, the devices manufactured by FDSOI naturally have the advantages of good short-channel effect control, low circuit static power consumption, stable threshold voltage and advanced body bias control technology. ...

AI Technical Summary

Problems solved by technology

[0006] The technical problem to be solved by the present invention is to provide a pseudo-gate removal method for FDSOI devices, which can solve the damage caused by phosphoric acid to the PMOS source-drain germanium-silicon layer and the chemical-mechanical polishing process in the existing process when the SiN sidewall is removed by wet method. The problem of large gate height difference

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