High-temperature surface acoustic wave device chip adopting array hole extraction electrode and manufacturing method of the high-temperature surface acoustic wave device chip
A technology for surface acoustic wave devices and extraction electrodes, which is applied in the manufacture/assembly of piezoelectric/electrostrictive devices, piezoelectric/electrostrictive devices, piezoelectric/electrostrictive/magnetostrictive devices, etc. Solve the problems of large device insertion loss, decreased mechanical properties, and difficult to remove photoresist, and achieve the effect of improving electrical reliability and reducing insertion loss
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Embodiment 1
[0047] A high-temperature surface acoustic wave device chip using an array hole to extract electrodes, in which a substrate 1, a seed layer 2, a bottom electrode 3, a piezoelectric film 4, an upper electrode 5, an isolation layer 6, and a top metal 7 are sequentially arranged from bottom to top, The upper electrode includes an interdigital transducer and a reflection grid, and its cross-sectional view is shown in figure 1 As shown, the top view is as figure 2 shown.
[0048] There is a channel I8 between the bottom electrode and the top metal, and the channel I is composed of three parts: the array hole I10 in the isolation layer, the hollow part in the upper electrode, and the array hole II11 in the piezoelectric film; the upper electrode There is another channel II9 between the top metal and the channel II, and the channel II is an array hole III12.
[0049] The shape of the holes in the array hole in the chip can be set to be square or circular, and there is no need to w...
Embodiment 2
[0053] A method for manufacturing a high-temperature surface acoustic wave device chip using array holes to lead out electrodes, the process of which is as follows image 3 shown, including the following steps:
[0054] S1: Prepare the SiC substrate and clean it with standard 1# and 2# solutions;
[0055] S2: AlN is deposited by sputtering on the polished surface of the SiC substrate;
[0056] S3: Sputtering depositing Mo on the AlN seed layer;
[0057] S4: Sputter deposition of pure AlN with c-axis orientation on the Mo bottom electrode;
[0058] S5: Sputtering depositing Cu on the AlN piezoelectric thin film;
[0059] S6: Stepper photolithography, RIE etching (reactive ion etching) Cu upper electrode, forming interdigital transducer and reflective grid structure;
[0060] S7: Suss photolithography, ICP etching (inductively coupled plasma etching) AlN piezoelectric film, forming array hole II in channel I, exposing the bottom electrode;
[0061] S8: PECVD (Plasma Enhance...
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