Preparation method of TSV (Through Silicon Via) with high depth-to-width ratio

Abstract

The invention relates to a preparation method of a TSV (Through Silicon Via) with a high depth-to-width ratio. The preparation method comprises the steps of step 1, carrying out via carving on a silicon wafer; 2, thinning the silicon wafer; 3, conducting deposition from the front side and the back side of the via; and 4, respectively performing metal filling from the front side and the back side of the via. Compared with the prior art, the preparation method of the TSV with the high depth-to-width ratio directly performs thinning treatment after the via is prepared on the silicon wafer, then performs the subsequent process treatment from the front side and the back side, thereby not only being higher in efficiency under the premise that the metal filled in the TSV is uniform, but also being capable of improving the depth-to-width ratio of the TSV, improving the circuit integration density, being better in filling quality, and facilitating the improvement of the integration density of electronic devices.

Description

technical field [0001] The invention belongs to the technical field of semiconductor packaging, and in particular relates to a method for preparing a TSV through-silicon via with a high aspect ratio. Background technique [0002] With the increasing scale of system integrated chips, three-dimensional integration technology can effectively reduce the circuit board area occupied by microsystem products in the horizontal direction, and at the same time reduce the length of interconnection lines and signal delay, so that the system has a small Advantages of size, high performance, and low power consumption. [0003] TSV (through silicon via) technology is the abbreviation of through-silicon via technology, generally referred to as through-silicon via technology, and is a technical solution for interconnection of stacked chips in three-dimensional integrated circuits. TSV technology has the advantages of small volume, high density, high integration, and small interconnection del...

AI Technical Summary

Problems solved by technology

In addition, the TSV structure formed by Via last technology is usually partially filled, and the bottom of the hole and the connection part of the pad are thin, which is easy to cause problems such as delamination and fracture, and the lack of dielectric layer filling protection will cause metal failure due to oxidation, corrosion and stress

[0006] When preparing through holes, a large aspect ratio means that the integration density of electronic devices can be increased, but a large aspect ratio will also make it difficult to fill copper, it is difficult to fill to the bottom of the through hole, and the deeper the filled area It is also more prone to uneven filling

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