Three-dimensional integrated circuit structure of large-area-array high-frame-frequency high-reliability miniaturized image sensor

Abstract

The invention relates to a three-dimensional integrated circuit structure of a large-area-array high-frame-frequency high-reliability miniaturized image sensor. The three-dimensional integrated circuit structure comprises a substrate, a cavity is arranged on the upper surface of the substrate, and a pixel chip is arranged in the cavity. The pixels in the pixel chip are longitudinally led out so that the area consumed by wiring of the pixel chip is saved, the capacity of weak light or low light imaging can be improved by increasing the sizes of the pixels, and the sensitivity of the chip is improved; higher resolution can be obtained by increasing the number of pixels, and the system integration degree is improved; the number of channels is increased by the added transverse leading-out of the pixels, the clock arrangement complexity can be effectively reduced, the system integration degree is improved, and the reliability of signal transmission is improved. The pixel chip is arranged inthe substrate with the cavity, and a filling agent is arranged so that the data transmission speed is increased, and the system frame frequency is increased; moreover, the coupling between the channels is reduced, and the signal-to-noise ratio is improved.

Description

Technical field [0001] The invention belongs to the field of semiconductor technology, and specifically relates to a three-dimensional integrated circuit structure of a large-area array, high frame rate, high reliability, and miniaturized image sensor. Background technique [0002] In traditional technology, the pixel unit and the readout circuit of the image sensor chip need to be manufactured on the same substrate, which not only reduces the filling rate of the pixel unit, but also causes the complexity of timing design and clock arrangement due to uneven signal line delays. Increase, the frame rate is low, and the output dynamic range is not high; in order to save the chip area, the area of ​​the wiring channel is compressed, which causes the crosstalk of the signal lines to increase and the signal-to-noise ratio decreases; at the same time, because the area array unit and the wiring channel occupy a large area of ​​the overall chip, However, more processing circuits cannot be...

AI Technical Summary

Problems solved by technology

[0002] In the traditional technology, the pixel unit and the readout circuit of the image sensor chip need to be manufactured on the same substrate, which not only reduces the filling rate of the pixel unit, but also causes the complexity of timing design and clock arrangement due to the uneven delay of the signal line. increase, the frame rate is low, and the output dynamic range is not high; in order to save the chip area, the area of ​​the wiring channel is compressed, causing the crosstalk between the signal lines to increase and the signal-to-noise ratio to decrease; at the same time, because the area array unit and the wiring channel occupy a large area of ​​the overall chip, Instead of integrating more processing circuits, which limits the function of the readout circuit, the system needs to adopt a two-dimensional integration method to improve its performance

The overall system volume is increased, the influence of parasitic effects becomes larger, and the system complexity increases, which is not conducive to miniaturization and integration, and is not conducive to the use of low noise and high frame rate; in order to improve system performance, it is necessary to adopt better technology and increase cost

[0003] In addition, although the performance of the system can be improved through three-dimensional integration in the prior art, problems such as dark current, crosstalk and warpage cannot be ignored.

In order to reduce the dark current, the pixel chip needs to adopt a larger pixel size, and the working speed is also low, which makes the system have low resolution, poor definition, and large size, which limits the application of large area array pixel chips; Reduce crosstalk, often by extending the lifetime of silicon carriers and improving silicon processing technology

Prolonging the lifetime of carriers will certainly improve quantum efficiency, but crosstalk will increase due to charge diffusion; methods to improve silicon processing technology increase system manufacturing costs

Due to the mismatch of thermal expansion coefficients of various materials in 3D integration, the number of chip stacks is limited, system performance is reduced, and system reliability is deteriorated

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