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Power discrete device adopting multi-chip stacked structure and preparation method of power discrete device

A discrete device and stacking structure technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electric solid-state devices, etc., can solve problems such as difficult chip stacking and packaging, and the inability of adhesive to meet thermal conductivity requirements.

Active Publication Date: 2020-10-20
华羿微电子股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] In the packaging process of GaN (gallium nitride) or SiC (silicon nitride) power discrete devices with multi-chip stacking structure, due to the existence of high current and high voltage, ordinary die-bonding adhesives cannot meet the heat conduction requirements. It is difficult to achieve chip stack packaging. In order to realize the miniaturization of the packaging structure, ensure heat dissipation and improve the withstand voltage performance of the device, it is necessary to develop a new device structure and use new packaging materials to ensure the reliability of the device.

Method used

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  • Power discrete device adopting multi-chip stacked structure and preparation method of power discrete device
  • Power discrete device adopting multi-chip stacked structure and preparation method of power discrete device
  • Power discrete device adopting multi-chip stacked structure and preparation method of power discrete device

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Embodiment 2

[0076] The second embodiment is an improvement of the first embodiment. In the first embodiment, please refer to the appendix for details. figure 1 , the first power chip and the second power chip and the lead frame are directly connected with the second aluminum strip 8 and the third aluminum strip 9, and when the heat dissipation substrate is bonded to the lead frame carrier, there will be adhesive overflow, which will affect the aluminum strip. Welding reliability. In the process of chip loading, it is necessary to strictly control the glue creep and glue overflow of the nano-sintered silver paste of the chip and the heat dissipation substrate. If the glue overflow exceeds the range, it will affect the welding area of ​​the aluminum strip, resulting in poor welding of the aluminum strip and circuit failure. In the second embodiment, by optimizing the design of the heat dissipation substrate, a via hole is arranged on the edge of the heat dissipation substrate, so that the u...

Embodiment 1

[0111] Embodiment one includes the following specific steps:

[0112] 1. Wafer thinning

[0113] In this embodiment, the thickness of the gallium nitride wafer reaches about 1000 μm, and the surface of the wafer is uneven. The thickness reaches 200μm, and the UV film completely covers the wafer to make the surface of the wafer flat and prevent water from entering, and then use the wet polishing process to thin the wafer to 350μm with a thinning machine. Since gallium nitride chips are relatively brittle and easy to crack, the thinning speed is one-half to one-third that of ordinary wafers, and the pressure is doubled. The polishing amount reaches more than 1.5 microns, which can eliminate the damage and stress caused by the polishing on the back of the wafer, and improve the cracking situation. In the present invention, silicon chips and silicon carbide chips do not need to be thinned.

[0114] 2. Scribing

[0115] When the selected chip is gallium nitride or silicon carbi...

Embodiment 3

[0137] The specific steps included in the packaging of the third embodiment refer to the first embodiment, except that the first chip is bonded to the heat dissipation substrate first, and the second chip is bonded to the first chip after baking. Carry out baking again, all the other technological processes are as embodiment one.

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Abstract

The invention belongs to the technical field of power device packaging structures, and particularly relates to a power discrete device adopting a multi-chip stacked structure and a preparation methodof the power discrete device, the power discrete device adopting the multi-chip stacked structure comprises a heat dissipation substrate; at least two chips which are respectively bonded on the heat dissipation substrate or are bonded on the heat dissipation substrate in a stacking manner, wherein conductive silver paste layers are arranged between the at least two chips and the heat dissipation substrate or between the at least two chips, and the adhesive dispensing patterns of the conductive silver paste layers are star-shaped or cross-shaped. The preparation method of the power discrete device adopting the multi-chip stacked structure can be used for preparing the power discrete device adopting the multi-chip stacked structure. According to the power discrete device adopting the multi-chip stacked structure and the preparation method of the power discrete device, the heat dissipation requirement of the power device can be guaranteed, and the purpose of the miniaturization of a high-power device packaging structure is achieved.

Description

technical field [0001] The invention belongs to the technical field of power device packaging structures, and in particular relates to a power discrete device using a multi-chip stack structure and a preparation method thereof. Background technique [0002] In recent years, the third-generation semiconductor materials (mainly including SiC, GaN, diamond, etc.) are becoming the focus of competition in the global semiconductor market with their superior performance and huge market prospects. Compared with the first and second generation semiconductor materials, the third generation semiconductor materials have the advantages of high thermal conductivity, high breakdown field strength, high saturation electron drift rate and high bonding energy, which can meet the requirements of modern electronic technology for high temperature and high power. , high voltage, high frequency and new requirements for harsh conditions such as radiation resistance, are promising materials in the f...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L25/18H01L23/495H01L23/367H01L23/373H01L21/50H01L21/60
CPCH01L25/18H01L23/49575H01L23/49524H01L23/4952H01L23/367H01L23/3735H01L21/50H01L24/84H01L24/85H01L2224/48247H01L2224/73265H01L2224/0603H01L2224/40245H01L2924/181H01L2224/32245H01L2224/48091H01L2224/73221H01L2924/00012H01L2924/00014H01L2924/00
Inventor 杨伊杰蒋卫娟缑娟孙炎权
Owner 华羿微电子股份有限公司