Preparation method of medium-voltage shield gate field effect transistor

Abstract

The invention provides a preparation method of a medium-voltage shield gate field effect transistor, which adopts silicon dioxide (SiO2)/silicon nitride (SiN)/silicon dioxide (SiO2) (ONO structure for short) as a trench barrier layer (ONOHardmask for short), prevents a thick oxygen step difference from being generated in a transition region on the surface of a substrate, and eliminates the hidden danger of electric leakage between a gate electrode and a source electrode.

Description

Technical field[0001]The present invention relates to the field of transistors, and more particularly to a method of preparing a medium pressure shield gate effect transistor.Background technique[0002]Medium pressure shield gate effect transistor (SGT) trench inverse oxygen thickness generally requires 3000 angstroms (the higher the device withstand voltage requirements, the field oxygen), the corresponding scheme needs to be selected during the manufacturing process to prevent the formation protection ring The paralysis difference between the transition area is too high, resulting in control of the control gate polysilicon residue. At present, the groove etch barrier layer in the medium pressure SGT manufacturing process mainly uses silica. After the trench is etched, the thick field oxygen mentioned above after the layer of silica is removed after the groove is etched. Outside the sidewall and bottom, the active region (Active) silicon surface also produces silica similar to thick...

AI Technical Summary

Problems solved by technology

After the polysilicon is filled in the trench, chemical mechanical polishing (CMP) is used to polish off the polysilicon and thick oxygen in the active area to eliminate the thick oxygen step in the above-mentioned transition area, and leave residues after the control gate polysilicon is etched in the subsequent process. Leakage between gate and source, this method requires polysilicon grinding equipment, and the process cost is high

If polysilicon is etched by low-cost dry etching method without using CMP equipment, due to the high selectivity ratio of etching to polysilicon and the underlying silicon dioxide, silicon dioxide will not be etched basically. The thick silicon dioxide on the active area will be removed by wet etching after definition by photolithography, but the thick silicon dioxide in the range of the terminal guard ring and the source polysilicon that is at the same potential as the active area cannot be removed, so in the same way as Thick oxygen steps will be formed in the transition region of the original cell. To eliminate the problem of control gate polysilicon residue, more excessive etching is required, which will cause the thickness of the control gate polysilicon in the trench of the original cell area to be very thin, and the metal connection via hole of the control gate It is easy to cut through and destroy the silicon dioxide isolation layer between the shield gate (connected to the source) and the control gate, which brings the same risk of gate-source leakage. In addition, excessive etching of the control gate will also cause channel The length becomes shorter, causing large threshold voltage fluctuations

This kind of process requires a high degree of matching with the device layout design, and the process control is difficult

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