TSV electroplating solution for chip 3D heterogeneous integrated packaging

Abstract

The invention relates to the technical field of semiconductor wafer level packaging, in particular to a TSV electroplating solution for chip 3D heterogeneous integrated packaging. The TSV electroplating solution is formed by uniformly mixing copper sulfate, sulfuric acid and chloride ions with three additives of CZ609A, CZ609B and CZ609C according to a certain proportion, the electroplating solution needs to be used at a stable temperature ranging from 22 DEG C to 28 DEG C, and is matched with proper equipment, and proper current density parameters are set, so that void-free filling, namely TSV complete filling, in a hole is finally achieved. The TSV electroplating solution has the characteristics that the TSV electroplating solution is stable in performance, ultra-long in service life and suitable for various hole patterns, the maximum use depth-diameter ratio of the hole pattern reaches 15: 1, and particularly, the TSV hole patterns with narrowed orifices caused by heterogeneous integration can still be perfectly filled.

Description

technical field [0001] The invention relates to the technical field of semiconductor wafer level packaging, in particular to a TSV electroplating solution for chip 3D heterogeneous integrated packaging. Background technique [0002] At present, the application of copper interconnect materials in wafer-level advanced packaging includes: copper through-silicon via (TSV), copper pillar (Pillar), copper bump (copper bump) and copper redistribution process (RDL) in 3D packaging. Ultra-pure copper interconnect coating liquid and additives are important materials for Damascene copper interconnection (Damascene copper interconnection process) process for manufacturing high-end chips with wafers above 8 inches and below 130 nanometers. [0003] Among them, compared with the traditional two-dimensional wire-bonded chip packaging technology, TSV copper can perform three-dimensional stacked packaging through silicon wafer through holes (Through Silicon Via-TSV), that is, multiple chips ...

AI Technical Summary

Problems solved by technology

[0004] TSV electroplating filling is the difficulty of the entire TSV process. In wafer-level 3D packaging, it is generally used to etch holes with different depths on the silicon wafer by first exposing and then dry etching. After the growth of the barrier layer, a layer of PVD is performed. Titanium is used to block the migration between copper atoms and silicon wafers. Finally, a layer of copper bell sub-layer is applied on PVD and enters the electroplating filling hole. After the electroplating process completes the void-free filling in the TSV hole, it enters the next CMP thinning process. In some high-frequency fields, such as 5G, due to its very high frequency, if only silicon is used, its anti-breakdown performance cannot meet the requirements of high-frequency use. Therefore, some impact-resistant materials will be grown on the silicon wafer to modify the chip. For example, a layer of silicon dioxide or silicon nitride barrier layer is grown on the surface of silicon to improve the service life of the chip under high-frequency conditions. As mentioned earlier, the TSV hole is etched by dry method, and the etching rate between different materials is different. The difference will appear in dry etching. The etching rate of the barrier layer is lower than that of the silicon single layer, resulting in narrowing of the aperture, which is a fatal effect on TSV plating filling.

At present, some foreign chip material suppliers have developed electroplating solutions suitable for super TSV hole filling, such as Rohm and Haas, etc., but they can only achieve hole shapes with a depth of about 100um and a depth-to-diameter ratio of less than 10:1. Solve the problem that TSV orifice narrowing due to heterogeneous integration can still achieve void-free filling

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