Preparation method of vertical nanowire array

Abstract

The invention relates to a preparation method of a vertical nanowire array, which comprises the following steps of: forming a nanoscale two-layer side wall cross array by adopting a two-time self-aligned side wall transfer technology, forming a silicon nitride nano dot array by utilizing the selection ratio of silicon oxide to silicon nitride and reactive ion etching (RIE) of the height difference of the cross position of the secondary side wall array, preparing a silicon nitride dot matrix array, etching substrate silicon by taking the silicon nitride dot matrix array as a mask to form a vertical nanowire array, and finally corroding residual silicon nitride and silicon oxide by using an acid solution to prepare the high-purity, damage-free, orderly and vertically arranged silicon nanowires.

Description

technical field [0001] The invention relates to the technical field of semiconductor integration, in particular to a preparation method of a vertical nanowire array. Background technique [0002] Vertical nanowires (V-SiNWs) are key structures for the fabrication and development of transistors, MEMS, optical sensors, and silicon-based batteries. Vertical silicon nanowire arrays, a special silicon nanostructure, have shown great potential in next-generation photovoltaic, photocatalytic, and sensor devices. [0003] However, at present, the preparation methods of V-SiNW arrays include electron beam lithography and etching, vapor-liquid-solid (VLS) synthesis, solution-liquid-solid (SLS) synthesis, reactive ion etching and metal-assisted chemical etching. Preparation of silicon nanowires. Electron beam exposure and etching schemes have low preparation efficiency and high cost, and cannot be used for large-scale preparation and application; VLS synthesis can prepare single-crys...

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Problems solved by technology

Electron beam exposure and etching schemes have low preparation efficiency and high cost, and cannot be used for large-scale preparation and application; VLS synthesis can prepare single-crystal silicon nano-nanowires. During the synthesis process, the metal catalyst gold will diffuse into the nanowires, affecting the nanostructures. The electrical properties of the wires are not compatible with cmos; the preparation of dispersed silicon nanowires by the solution-liquid-solid (SLS) method has the advantages of low cost and large-scale production potential, but it is difficult to prepare highly ordered VA-SiNW arrays; metal Silicon nanostructures with high structural fidelity and purity can be fabricated by metal-assisted chemical etching (MACE), however, it is difficult to control the size and uniformity of nanoarrays by metal-assisted chemical etching

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