Neuron structure based on partially depleted silicon-on-insulator and working method thereof
A silicon-on-insulator, depletion-type technology, applied in the field of neuron structure, can solve the problems of incompatibility of CMOS synapses, large unit area occupation, complex manufacturing process, etc., to achieve increased integration density, reduced occupied area, and simple manufacturing process Effect
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Embodiment 1
[0042]In this embodiment, the gate length of the NMOS PD-SOI transistor 1 is 5nm-1um, so as to ensure that the leakage caused by the input current will not affect the spike characteristics of the LIF neurons. Longer gate lengths result in higher peak voltages and improved noise margins, but at the same time lead to higher power dissipation.
Embodiment 2
[0044] In this embodiment, the NMOS PD-SOI transistor 1 is fabricated on an SOI wafer with a buried oxide layer thickness of 10nm-1um. The thickness of the buried oxide layer must ensure that the device is isolated from the outside world, so that the current source can operate on a single device without affect other devices.
Embodiment 3
[0046] In this embodiment, the output current of the constant current source 3 is 10pA~100nA. Since the transistor structure itself has a certain leakage, the normal charging step may not be realized if it is lower than 10pA, and the transistor may be damaged if it is higher than 100nA. The breakdown of the pn junction in the cell prevents normal neuron characteristics from being displayed. At the same time, the size of the current source will affect the frequency characteristics of the spike.
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