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Mirror bit SONOS flash memory unit

A flash memory cell and mirror technology, applied in electrical components, electrical solid-state devices, circuits, etc., can solve problems such as difficulties, and achieve the effects of reducing process costs, saving lithography processes, and improving chip integration.

Pending Publication Date: 2022-03-01
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The channel of the entire memory cell is very short, and it becomes very difficult to perform individual threshold voltage adjustment ion implantation for the channel of the memory
This further limits the size reduction of the SONOS Flash unit

Method used

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  • Mirror bit SONOS flash memory unit
  • Mirror bit SONOS flash memory unit
  • Mirror bit SONOS flash memory unit

Examples

Experimental program
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Effect test

Embodiment Construction

[0040] like figure 1 shown is a schematic structural diagram of a mirror-bit SONOS flash memory cell according to an embodiment of the present invention; the mirror-bit SONOS flash memory cell according to the embodiment of the present invention includes a selection transistor and a storage transistor, and the selection transistor is an enhancement-mode MOS transistor and has a first threshold voltage, The storage transistor is a depletion-mode SONOS storage transistor and has a second threshold voltage in a state where no charge is stored.

[0041] The selection transistor and the storage transistor share a heavily doped source region and a drain region of the first conductivity type formed on the semiconductor substrate 101, and a surface of the semiconductor substrate 101 between the source region and the drain region is formed with a first conductivity type. A lightly doped channel doping layer 103 of conductivity type. In the embodiment of the present invention, the sour...

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PUM

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Abstract

The invention discloses a mirror bit SONOS flash memory unit, which comprises a selection tube and a storage tube, the selection tube is an enhanced MOS transistor and has a first threshold voltage, and the storage tube is a depletion type SONOS storage transistor and has a second threshold voltage in a state of not storing charges. The selection tube and the storage tube share a first conduction type heavily-doped source region and a first conduction type heavily-doped drain region, and a first conduction type lightly-doped channel doping layer is formed between the source region and the drain region. And a first gate structure of the selection tube and a second gate structure of the storage tube are arranged on the channel doping layer. The first gate conductive material layer of the first gate structure has a first work function, and the second gate conductive material layer of the second gate structure has a second work function. The first threshold voltage is adjusted by the first work function, and the second threshold voltage is adjusted by the second work function. According to the invention, the forming process of the channel doping layers of the selection tube and the storage tube can be simplified, and the channel lengths of the whole selection tube, the storage tube and the whole unit can be reduced.

Description

technical field [0001] The present invention relates to a semiconductor integrated circuit, in particular to a Mirror-Bit SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) flash memory (Flash) unit. Background technique [0002] Mirror-Bit SONOS Flash is usually composed of an enhanced NMOS selection transistor and two left-right symmetrical depletion-mode N-type SONOS memory devices, namely depletion-mode memory. [0003] In order to obtain a depletion-type memory, it is necessary to ion-implant N-type impurities in a P well (Pwell) to adjust the initial threshold voltage of the memory to a negative value. [0004] The 1.5T Mirror-Bit SONOS Flash unit adopts a structure in which the memory channel and the selection tube channel are closely connected, and the selection tube has no separate source and drain regions. The channel of the entire memory cell is very short, and it becomes very difficult to perform individual threshold voltage adjustment ion implantation for the channel ...

Claims

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Application Information

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IPC IPC(8): H01L27/1157H01L27/11568
CPCH10B43/30H10B43/35
Inventor 钱文生
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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