Check patentability & draft patents in minutes with Patsnap Eureka AI!

Floating gate type split gate flash memory process method

A process method and floating gate technology, applied in the direction of electrical components, electrical solid devices, circuits, etc., can solve the problems of poor compatibility and achieve the effects of reducing process manufacturing costs, increasing compatibility, and reducing resistivity

Pending Publication Date: 2022-03-11
HUA HONG SEMICON WUXI LTD +1
View PDF0 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The particularity of the 3-fold self-alignment process of 2-bit / cell split-gate floating-gate flash memory makes the height of the flash memory cell much higher than that of CMOS devices, making its compatibility worse

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Floating gate type split gate flash memory process method
  • Floating gate type split gate flash memory process method
  • Floating gate type split gate flash memory process method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0041] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0042] see Figure 1-11 , in an embodiment of the present invention, a floating gate split-gate flash memory process method, including 101—a medium-high voltage P-type well formed on a substrate, 102—a floating gate dielectric layer silicon oxide, 103—a floating gate polysilicon layer, 104—ONO dielectric stack between polysilicon, 104-1—silicon oxide layer, 104-2—first silicon nitride layer, 104-3—top silicon oxide layer, 105—first sidewall control gate polysi...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a floating gate type split gate flash memory process method. The process method comprises the following steps: S1, defining a floating gate flash memory and an active region of a peripheral logic region; s2, removing the silicon nitride layer, and sequentially forming a silicon oxide layer, a silicon nitride layer, a sacrificial silicon oxide layer and a silicon nitride layer; s3, depositing to form a polycrystalline silicon layer, and performing anisotropic etching to form a first side wall control gate; s4, depositing and etching to form a second side wall dielectric layer; s5, etching to remove the floating gate polycrystalline silicon layer in the opening; s6, thermal oxidation is carried out to form protective etching at the top end of the selection grid polycrystalline silicon layer; s7, performing injection to form a lightly doped drain Halo ion injection layer; and S8, performing source-drain heavily-doped injection to form a source-drain heavily-doped ion injection layer. According to the control gate, first side wall control gate polycrystalline silicon is formed through isotropic deposition and anisotropic etching of a polycrystalline silicon layer; according to the invention, the initial height of the lamination can be reduced; in addition, because the first side wall control gate and the floating gate are made of the same material, part of the control gate polycrystalline silicon layer is etched at the same time during the first etching of the floating gate, and the height of the Cell is further reduced; therefore, the compatibility of the flash memory device and an advanced process is improved; in the subsequent process, metal silicide can be simultaneously formed on the top of the polycrystalline silicon with the selection gate, so that the on resistance of the control gate is reduced, and the integration level of the flash memory is improved.

Description

technical field [0001] The invention relates to the technical field of flash memory, in particular to a process method of floating gate split-gate flash memory. Background technique [0002] Flash memory is a non-volatile memory, and data will not be lost even if the power is turned off. Because flash memory does not rewrite data in units of bytes like RAM (Random Access Memory), it cannot replace RAM. Flash Card is a memory that uses Flash Memory technology to store electronic information. It is generally used as a storage medium in digital cameras, handheld computers, MP3 and other small digital products, so it looks small and compact, like a card, so Call it a flash card. According to different manufacturers and different applications, flash memory cards generally include SmartMedia (SM card), Compact Flash (CF card), MultiMediaCard (MMC card), Secure Digital (SD card), Memory Stick (memory stick), XD-PictureCard Although these flash memory cards (XD card) and micro ha...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11521H01L27/11517H10B41/30H10B41/00
CPCH10B41/00H10B41/30
Inventor 许昭昭陈华伦钱文生
Owner HUA HONG SEMICON WUXI LTD
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More