Narrow-band-gap semiconductor device and preparation method thereof

Abstract

The invention provides a narrow-band-gap semiconductor device with a high switch ratio and a manufacturing method of the narrow-band-gap semiconductor device. The device is provided with a supporting substrate, a narrow-band-gap semiconductor layer, a gate dielectric layer and a gate stacking structure are sequentially arranged on the supporting substrate, and L-shaped self-alignment side walls are arranged on the two sides of the gate stacking structure. And the horizontal part and the gate dielectric layer below the horizontal part respectively extend towards the source region and the drain region at the outer side for a certain length along the plane where the narrow-band gap semiconductor layer is located. Metal is further deposited on the horizontal part of the outer side of the side wall and the narrow-band-gap semiconductor layer, and the narrow-band-gap semiconductor layer is used as a source electrode and a drain electrode of the semiconductor device. According to the device, a side wall is formed through a grid electrode self-alignment technology, the electric field intensity at the junction of a channel and a source and drain electrode region can be reduced, the width of a tunneling potential barrier between drain electrode end bands is increased, reverse tunneling of drain electrode end minority carriers can be well restrained when the device works under large bias voltage, and the reliability of the device is improved. Therefore, the switching ratio can be increased while the high performance of the narrow-band-gap semiconductor device is maintained, and the bipolar is remarkably suppressed.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a field-effect transistor with carbon nanotubes and a manufacturing method thereof. Background technique [0002] At present, the feature size of key patterns of advanced silicon-based integrated circuit devices has crossed the 10nm mark. When transistors continue to develop to 5nm or even smaller node technology, it is foreseeable that silicon-based semiconductor technology is being affected by processing technology, device physics Limit, performance and other challenges, its continued development must overcome huge obstacles in terms of power consumption and cost, and the development space is becoming smaller and smaller. It is urgent to find new information devices to continue to promote the development of the future semiconductor industry. [0003] In recent years, many new semiconductor materials have great development potential in the field of hig...

AI Technical Summary

Problems solved by technology

However, due to the small bandgap, when working in the off state, the minority carrier tunneling at the drain is very serious

In addition, this kind of feedback gate also has many shortcomings in the process. Because it adopts a non-self-aligned process, there is a large alignment deviation problem, and it is not compatible with the current integrated circuit manufacturing process, so it cannot be mass-produced.

In addition, the drain terminal occupies a large contact area, and it is difficult to continue to shrink with the development of semiconductor technology nodes.

[0007] In addition, IBM reported an asymmetric contact structure, which widens the Schottky barrier into a triangular barrier by etching near the drain end, thereby increasing the switching ratio. However, the drain end barrier of this method There is still a thinning trend with increasing bias voltage

In addition, this method is also a non-self-alignment process, which has alignment problems, and the structure is complicated to prepare and the controllability of wet etching is poor. The uniformity and stability of device performance are challenged, and it is not easy to integrate.

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