Unlock instant, AI-driven research and patent intelligence for your innovation.

Method for manufacturing silicon swfer, silicon wafer and SOI wafer

A manufacturing method and technology for silicon wafers, which are applied in the field of manufacturing silicon wafers, and can solve the problems of increasing the number of processes, deteriorating flatness, and the like

Inactive Publication Date: 2004-04-14
SHIN-ETSU HANDOTAI CO LTD
View PDF4 Cites 10 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this etching method, acid etching is performed after alkaline etching, and the surface roughness of the wafer can be reduced, but on the other hand, there is a problem that the flatness is slightly deteriorated due to acid etching, or the number of steps is increased.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Method for manufacturing silicon swfer, silicon wafer and SOI wafer
  • Method for manufacturing silicon swfer, silicon wafer and SOI wafer
  • Method for manufacturing silicon swfer, silicon wafer and SOI wafer

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1～3 and comparative example 1～5

[0119] First, a p-type single crystal ingot with a diameter of 200 mm (8 inches) and a resistivity of about 8 to 10 Ω·cm is produced by the CZ method. Prepare the silicon wafer, the silicon wafer in accordance with figure 1 In the process shown, the obtained ingot is cut with a wire saw, and the peripheral part is chamfered.

[0120] Then, the silicon wafer prepared as described above is polished in a polishing process.

[0121] This polishing is used as Figure 5 Polishing device shown. In addition, two kinds of FO abrasive grains, namely, abrasive grain #1500 and FO abrasive grain #1200, which are abrasive grains FO manufactured by Fujimi Co., Ltd., were used as free abrasive grains, and they were supplied at 1.5 L / min from a nozzle and polished. The polishing treatment range is approximately 70 μm on both sides of the silicon wafer. According to the processing, two types of polished wafers are obtained.

[0122] Then, using a primary sodium hydroxide particle test agent manufa...

Embodiment 2

[0132] As a result of polishing the silicon wafer of Example 2, a polishing range of about 10 μm is a mirror wafer. This polishing range value is smaller than the polishing range (12 μm) in the polishing step of the conventional silicon wafer manufacturing method, and it can be seen that the polishing range can be reduced according to the present invention. Secondly, by testing the GBIR (Global Back Ideal Range) value of a plurality of mirror wafers obtained, and finding the average GBIR value to evaluate the flatness of the wafer.

[0133] GBIR generally has a reference surface in the chip, and the reference surface defines the maximum and minimum position shift amplitude, which is equivalent to the existing conventional style, that is, the value of TTV (total thickness deviation). For the measurement of flatness this time, a capacitance-type flat surface measuring device made by ADE company, ULTRA-GAUGE9900, was used for the measurement with the exception of 2mm around the wafer...

Embodiment 4 and comparative example 7、8

[0139] After making a silicon single crystal with a diameter of 20 mm, a p-type, and a resistivity of about 10 Ω·cm according to the CZ method, the silicon was made under the same processing conditions as in Example 2 above (free abrasive grain is FO#1500, NaOH concentration is 55.0% by weight) Wafer (Example 4). After that, the three parameters related to the silicon wafer, which indicate the upturn, sag, and fluctuation of the surface shape characteristics, were measured. The results of the measurement are as follows Picture 10 Shown. Here is a specific description of the method of measuring the upturn, sag, and fluctuation of the wafer.

[0140] First, in order to measure the upturn and sagging of the wafer, a silicon wafer with a diameter of 200 mm as the measurement object was measured using a capacitance type plane measuring device (ULTRAGAUGE 9900 manufactured by ADE) at intervals of 0.95 mm as the wafer evaluation surface (including The chamfered part is within 1mm from t...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
sizeaaaaaaaaaa
electrical resistivityaaaaaaaaaa
sizeaaaaaaaaaa
Login to View More

Abstract

A production method for a silicon wafer comprising a lapping process by at least free abrasive grains, and an etching process by an alkali etchant, characterized in that in the lapping process lapping is performed by using free abrasive grains having a maximum grain size of up to 21 mum and an average grain size of up to 8.5 mum, and then in the etching process etching is performed by using as an alkali etchant an alkali aqueous solution having an alkali component concentration of at least 50 Wt.% and a silicon wafer produced by this method. Accordingly, the production method that can prevent deterioration in wafer surface roughness and in flatness of a wafer as a whole, and a silicon wafer produced by the method are provided.

Description

Technical field [0001] The present invention relates to a method for manufacturing a silicon wafer, which can prevent dust generation and deterioration of flatness occurring in a silicon wafer manufacturing process, and particularly relates to a polishing process and an etching process. Background technique [0002] In the past, when manufacturing chips used in integrated circuits such as ICs or LSIs or discrete semiconductor components such as transistors or diodes, for example, according to Figure 7 The manufacturing process shown is carried out. For the silicon ingot grown by the Czochralski method (CZ method) or the floating zone method (FZ method), first, it is cut into a wafer shape in the dicing step (A) using a circular blade cutter, a wire saw, or the like. Secondly, in order to prevent the chip side of the wafer, after chamfering the outer edge of the wafer in the chamfering (chamfering) step (B), in order to improve the flatness, free abrasive grains are used on the w...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/304C09K13/02H01L21/302C09K13/08H01L21/306H01L21/762B24B37/00B24B37/04H01L21/02H01L21/308H01L27/12
CPCH01L21/02019C09K13/08C09K13/02H01L21/02008H01L21/30604Y10T428/12229H01L21/304
Inventor 饭塚人二本松孝吉田正彦宫崎诚一
Owner SHIN-ETSU HANDOTAI CO LTD