Low temp polycrystal silicon film transistor and manufacturing method thereof

A thin-film transistor and low-temperature polysilicon technology, which is applied in the manufacture of transistors, semiconductor/solid-state devices, electrical components, etc., can solve the problems of high manufacturing cost of low-temperature polysilicon thin-film transistors, complicated LDD process, etc. The effect of low leakage current

Active Publication Date: 2006-01-25
AU OPTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0008] It can be known from the above process that at least five photomasks are required to complete the existing low-temperature polysilicon thin film tra...

Method used

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  • Low temp polycrystal silicon film transistor and manufacturing method thereof
  • Low temp polycrystal silicon film transistor and manufacturing method thereof
  • Low temp polycrystal silicon film transistor and manufacturing method thereof

Examples

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no. 1 example

[0031] Figure 2A to Figure 2H Shown is a schematic cross-sectional view of the manufacturing process of a low-temperature polysilicon thin film transistor according to a preferred embodiment of the present invention. Please refer to Figure 2A Firstly, the gate electrode 202 , the gate dielectric layer 204 , the first amorphous silicon layer 206 and the patterned insulating layer 208 are sequentially formed on the substrate 200 . Wherein, the patterned insulating layer 208 is disposed on the first amorphous silicon layer 206 and located above the gate 202 . In this embodiment, the material of the patterned insulating layer 208 is, for example, silicon oxide or silicon nitride.

[0032] Please refer to Figure 2B , using the patterned insulating layer 208 as a mask to perform a doping process, such as performing an ion implantation process, to dope dopant ions 230 into the part of the first amorphous silicon layer 206 not covered by the patterned insulating layer 208 In or...

no. 2 example

[0042] Figure 3A to Figure 3C Shown is a schematic cross-sectional schematic diagram of part of the manufacturing process of a low-temperature polysilicon thin film transistor according to another embodiment of the present invention. Please refer to Figure 3A , according to the above Figure 2A to Figure 2D After the first patterned amorphous silicon layer 206a and the second patterned amorphous silicon layer 210a are completed, the source / drain layer is then formed on the substrate 200 and the second patterned amorphous silicon layer 210a 218. Here, the second patterned amorphous silicon layer 210a is an ohmic contact layer serving as a thin film transistor.

[0043] Please refer to Figure 3B , and then irradiated with, for example, an excimer laser beam 222 Figure 3A The completed structure is such that part of the first patterned amorphous silicon layer 206a located above the gate 202 is melted and recrystallized to form a polysilicon channel region 212, as Figur...

no. 3 example

[0046] Figure 4A to Figure 4B Shown is a cross-sectional view of part of the manufacturing process of a low-temperature polysilicon thin film transistor according to yet another embodiment of the present invention. Please refer to Figure 4A ,according to Figure 2A After the patterned insulating layer 208 is formed on the substrate 200 according to the above process, a second amorphous silicon layer 310 is formed on the first amorphous silicon layer 206 to cover the patterned insulating layer 208 . Wherein, the second amorphous silicon layer 310 may be an amorphous silicon layer with or without dopants.

[0047] Please refer to Figure 4B , followed by Figure 2D As described above, the first patterned amorphous silicon layer 206 a and the second patterned amorphous silicon layer 310 a are formed. Then, a doping process is performed by using the patterned insulating layer 208 as a mask to dope dopant ions 230 into part of the first patterned amorphous silicon layer 206a...

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Abstract

A low temperature poly-silicon film transistor includes a gate, a gate dielectric layer, a pattern silicon layer, a pattern insulation layer, an ohm contact layer and a source/drain layer. The gate and its dielectric layer are matched on the base plate and the silicon and the insulation layers are matched on the dielectric layer above the gate orderly. The pattern silicon layer includes a poly-silicon channel zone and a non-crystalline silicon thermal carrier suppression zone. The ohm contact layer is matched on part of the insulation layer above the dielectric layer and the thermal carrier suppression zone and connected with the suppressing zone set between the ohm contact layer and the poly-silicon channel the source/drain layer is matched on the gate dielectric and the ohm contact layer to suppress the thermal carrier effect.

Description

technical field [0001] The present invention relates to a structure of a transistor and a manufacturing method thereof, in particular to a low temperature polysilicon thin film (low temperature poly-silicon, LTPS for short) transistor and a manufacturing method thereof. Background technique [0002] In general components, switches are required to drive the operation of the components. Taking the active display element as an example, it usually uses a thin film transistor (Thin Film Transistor, TFT) as a driving switch. The thin film transistors can be further divided into amorphous silicon (a-Si) thin film transistors and polysilicon (poly-silicon) thin film transistors according to the material of the channel layer. In addition, thin film transistors can also be classified into top-gate TFTs and bottom-gate TFTs according to the relative positions of the channel layer and the gate. Since the bottom-gate thin film transistor has a less polluted interface (insulating layer / ...

Claims

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Application Information

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IPC IPC(8): H01L29/786H01L21/336
Inventor 郭政彰
Owner AU OPTRONICS CORP
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