Process to minimize and/or eliminate conductive material coating over the top surface of a patterned substrate

Abstract

A layer structure usable in manufacturing an integrated circuit is made, in a single apparatus, by a particular process in which a patterned substrate is provided. An electrolyte solution, out of which a conductive material can be plated under an applied potential, is supplied over a surface of the patterned substrate, and a potential is applied so as to deposit a film of the conductive material out of the electrolyte solution and over the surface of the patterned substrate. The film of conductive material is preferably polished as it is deposited. The conductive material is then removed from field regions of the patterned substrate, while deposits of the conductive material are left in features defined in the patterned substrate. The deposits of the conductive material are then electrically isolated, resulting in the layer structure.

Description

[0001] This application claims the priority of U.S. provisional application No. 60 / 198,371, filed Apr. 19, 2000, the disclosure of which is expressly incorporated by reference herein.BACKGROUND AND SUMMARY OF THE INVENTION [0002] Multi-level integrated circuit manufacturing requires many steps of metal or metal alloy and insulator film depositions followed by photoresist patterning and etching or other material removal operation. After photolithography and etching, the resulting wafer or substrate surface is non-planar and contains many features such as vias, lines or channels, test pads and bond pads. Often, these features need to be filled with a specific material such as a metal, and then the wafer topographic surface needs to be planarized, making it ready for the next level of processing. [0003] Electrodeposition is a widely accepted technique for depositing a highly conductive material such as copper (Cu) into the features on the semiconductor wafer surface. Chemical mechanica...

AI Technical Summary

Benefits of technology

[0007] Removal of the large and non-uniform overburden of FIG. 2 from the patterned substrate surface and obtaining the structure in FIG. 3 with minimal dishing is difficult, time consuming, and expensive. We have recently disclosed methods and apparatus that can plate and polish or minimize accumulation of metal or metal alloy overburden and, therefore, yield a film 8 of conductive material such as Cu, with a uniform overburden 8a as depicted in FIG. 4. In this application, we disclose a method that minimizes the thickness of this overburden and even eliminates it through the use of electrochemical etching or chemical etching. In known manufacturing processes, the CMP, chemical etching or electrochemical etching steps are typically carried out in an apparatus separate from the Cu deposition apparatus. One unique feature of the present invention is that all of the process steps are carried out in the same apparatus. This approach further allows Cu deposition selectively into the features and building up of the Cu overburden only over the features but not over the field regions. Such a structure is very desirable for minimizing dishing during the CMP process as will be explained later.

Problems solved by technology

The example shown demonstrates an especially challenging case of metal filling and planarization procedures which are carried out with patterned substrate features having widely different sizes.

Removal of the large and non-uniform overburden of FIG. 2 from the patterned substrate surface and obtaining the structure in FIG. 3 with minimal dishing is difficult, time consuming, and expensive.

However, this technique requires the use of several steps, i.e. deposition, planarization, and etching, carried out in different apparatus, making it very costly.

This would not be practical in a large category of wafers, which typically contain over 50 micron wide trenches and / or bond or test pads, as well as features with sub-micron size.

This is neither practical nor economical.

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