Cleaning solution formulations for substrates

Abstract

A semiconductor system includes: providing a dielectric layer; providing a conductor in the dielectric layer, the conductor exposed at the top of the dielectric layer; capping the exposed conductor; and modifying the surface of the dielectric layer, modifying the surface of the dielectric layer, wherein modifying the surface includes cleaning conductor ions from the dielectric layer by dissolving the conductor in a low pH solution, dissolving the dielectric layer under the conductor ions, mechanically enhanced cleaning, or chemisorbing a hydrophobic layer on the dielectric layer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This is a continuation application of U.S. patent application Ser. No. 11 / 760,722, filed Jun. 8, 2007, which claims the benefit of U.S. Provisional Patent Application Ser. No. 60 / 804,425 filed Jun. 9, 2006. The contents of U.S. patent application Ser. No. 11 / 760,722, filed Jun. 8, 2007, and the contents of U.S. Provisional Patent Application Ser. No. 60 / 804,425, filed Jun. 9, 2006, are incorporated herein, in their entirety, by this reference for all purposes.TECHNICAL FIELD[0002]The present invention relates generally to semiconductor systems, and more specifically to advanced semiconductor manufacturing systems and device systems.BACKGROUND ART[0003]Semiconductor devices are used in products as extensive as cell phones, radios, and televisions. The semiconductor devices include integrated circuits that are connected by conductive wires embedded in insulating material.[0004]With the reducing of semiconductor device size and the use of lo...

AI Technical Summary

Benefits of technology

The present invention provides a semiconductor system that includes a method for cleaning conductor ions from a dielectric layer and modifying the surface of the dielectric layer. This allows for improved performance and reliability of the semiconductor system.

Problems solved by technology

With the reducing of semiconductor device size and the use of low dielectric constant (low k) interlayer dielectric (ILD) insulating materials, obtaining reliable semiconductor devices is becoming more and more challenging.

In particular, reliability problems occur at interfaces of the copper (Cu) wires and low k ILD material in the form of leakage, electromigration, stress migration, break down voltage, and time dependent dielectric breakdown (TDDB), etc.

Cu easily diffuses into silicon (Si) and causes degradation of the dielectric material.

Cu is also susceptible to oxidation and corrosion.

However, the Cu / capping layer interface is still one of the major failure paths due to the weak adhesion between Cu and the capping layer.

The mobility of these contaminants cause high leakage currents, and may cause damage to the dielectric materials when they move along the interface.

Such process is known to decrease TDDB lifetime.

While there have been many attempts to improve device reliability by applying metal / metal alloy capping layer on copper interconnect, solutions to the problems related to interface reliability problems have been long sought, but have long eluded those skilled in the art.

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