Method for processing gate dielectric layer deposited on germanium-based or group III-V compound-based substrate

Abstract

The present invention discloses a method for processing a gate dielectric layer deposited on a germanium-based or Group III-V compound-based substrate, belonging to a semiconductor device field. The method comprises the steps of depositing a high-K gate dielectric layer on the germanium-based or Group III-V compound-based substrate, and then performing a plasma process to the high-K gate dielectric layer by using fluorine plasma, wherein during the plasma process, a guiding electric field is applied so that fluorine ions, when being accelerated to a surface of the gate dielectric layer, has an energy of 5-50 eV and the fluorine plasma drifts into the high-K gate dielectric layer, a ratio of a density of the fluorine ions in the high-K gate dielectric layer and a density of oxygen atoms in the high-K gate dielectric layer being 0.01-0.15:1.

Description

CROSS REFERENCE OF RELATED APPLICATIONS[0001]This application is a 371 U.S. Nationalization of Patent Cooperation Treaty Application PCT / CN2014 / 070302, filed Jan. 8, 2014 which claims the benefit of Chinese Patent Application No. 201310208388.X, filed on May 30, 2013, each of which are incorporated herein by reference in their entirety.FIELD OF THE INVENTION[0002]The present invention refers to a semiconductor device, and particularly refers to a method for processing a gate dielectric layer deposited on a germanium-based or Group III-V compound-based substrate.BACKGROUND OF THE INVENTION[0003]As the geometry size of the silicon-based metal-oxide-semiconductor field effect transistor (MOSFET) shrinks to a nanometer level, traditional methods to improve performance and integration degree by reducing the size of the transistor is facing dual limitation tests both in physical and technical aspects. In order to further improve the performance of the transistor, one of the effective meth...

AI Technical Summary

Benefits of technology

The present invention provides a better way to prepare a gate dielectric layer on Germanium or Group III-V compound substrates. By using a fluorine plasma passivation process, defects at the interface and within the gate dielectric layer are reduced. This is done by applying an electric field to guide the fluorine plasma towards the gate dielectric, resulting in a higher concentration of fluorine ions and a lower concentration of oxygen atoms in the gate dielectric layer. This enhances the quality of the gate dielectric layer and improves the efficiency and performance of the MOS devices.

Problems solved by technology

As the geometry size of the silicon-based metal-oxide-semiconductor field effect transistor (MOSFET) shrinks to a nanometer level, traditional methods to improve performance and integration degree by reducing the size of the transistor is facing dual limitation tests both in physical and technical aspects.

However, the current technologies for fabricating the germanium-based and Group III-V compound-based MOS devices are not yet matured.

If a high-K gate dielectric layer is deposited on a substrate directly, defects such as high interface state density and poor interface quality may be existed at the interface, affecting the performance of the germanium-based and Group III-V compound-based MOS devices.

Images