Silicon-on-insulator chip having an isolation barrier for reliability

Abstract

An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact—which define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This applicationis a Reissue Application of U.S. Pat. No. 6,492,684, issued Dec. 10, 2002, which is a continuation-in-part of U.S. patent application Ser. No. 09 / 859,146, filed on May 16, 2001 <?delete-start id="DEL-S-00002" date="20080527" ?>(pending)<?delete-end id="DEL-S-00002" ?> <?insert-start id="INS-S-00002" date="20080527" ?>now U.S. Pat. No. 6,563,173<?insert-end id="INS-S-00002" ?>, which is a continuation of U.S. patent application Ser. No. 09 / 148,918, filed on Sep. 4, 1998 (allowed), U.S. Pat. No. 6,281,095 which is a divisional of U.S. patent application Ser. No. 09 / 009,445; filed on Jan. 20, 1998, now U.S. Pat. No. 6,133,610.FIELD OF THE INVENTION[0002]The present invention relates generally to a silicon-on-insulator (SOI) chip and, more particularly, to an SOI chip having an isolation barrier to prevent the diffusion of impurities into active regions of the chip.BACKGROUND[0003]As the scale of int...

AI Technical Summary

Benefits of technology

[0015]To achieve these and other objects, and in view of its purposes, the present invention provides an SOI chip including a substrate, a buried oxide layer deposited above the substrate, and a silicon layer deposited above the oxide layer. A gate oxide layer is deposited above the silicon layer. A gate is deposited above the gate oxide layer. A gate metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The SOI chip has an isolation barrier extending through the silicon layer and the buried oxide layer to prevent diffusion of impurities into the buried oxide layer. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contact, to define an active chip area inside the isolation barrier.

Problems solved by technology

During the packaging of a semiconductor chip, impurities from the packaging environment can enter the chip, diffuse into silicon junctions, and compromise the reliability and performance of the integrated circuit.

Contamination at this particular juncture of the manufacturing process can result in loss of manufacturing yield.

The process of exposing the edges of SOI chips before dicing involves several potentially defect-producing steps which may reduce the overall manufacturing yield of the integrated circuits.

This leads to larger “footprint” or die sizes.

Larger die sizes often decrease the amount of chips available per wafer, causing manufacturing cost to increase.

Any break in the film would risk contamination of the final chip by mobile ions.

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