45 results about "Partial-response maximum-likelihood" patented technology

A partial response (PR) waveform generator generates a digital value sequence of an expected PR waveform based on the output of a soft-decision Viterbi detector included in, for example, a first-stage decoder unit incorporated in an iterative decoder. The generator also generates flag information indicative of whether reliability of the digital value sequence is low or high, in parallel with the generation of the digital value sequence. An error detector detects error values in a PR equalized sample value sequence, needed for feedback control of a control target, using the digital value sequence of the expected PR waveform as a digital value sequence of a reference waveform. An error output controller controls the output of the error values detected by the error detector in accordance with the state of the flag information generated by the generator.

A partial response maximum likelihood (PRML) data detecting in a magnetic recording storage device is carried out with a preliminary measuring of write-read channel responses to all nonzero binary combinations of a given length. Decoding of the user data is performed according to a Viterbi algorithm, where the previously measured responses are used as expected samples for branch metric calculations. The measurement of the write-read channel responses and the decoding of the user data are fulfilled by a self-adjusting PRML receiver that contains a controllable clock recovery, a responses accumulator and an adjustable Viterbi detector. The controllable clock recovery produces a set of read-back signal samples containing exactly one sample per bit with or without phase error correction. The responses accumulator calculates averaged responses of the write-read channel. The adjustable Viterbi detector reconstructs the user data that were written to the disk.

In a digital data reproduction apparatus for demodulating digital data from an optical recording medium, PRML (Partial Response Maximum Likelihood) signal processing effective to high-density recording/reproduction is carried out by using a half rate processing offset control means which performs data demodulation using half of the channel bit frequency, a half rate processing phase sync control means, a half rate processing adaptive equalization means, and a half rate processing maximum likelihood decoder, and the digital data recorded on the optical recording medium are reproduced while restoring signal components which are missing in the time direction, by linear interpolation or Nyquist interpolation. Therefore, digital data reproduction performance is improved, and power consumption is reduced.

The invention relates to a variable parameter self-adaptive PRML (Partial Response Maximum Likelihood) data sink for a high density optical disk storage system on the basis of freedom clock sampling and a data processing method thereof. The data sink comprises a free clock sampling module, a variable parameter self-adaptive signal conditioning module, a clock recovering module, a self-adaptive maximum likelihood coding module and a target response selecting module; according to the invention, by adopting a variable parameter self-adaptive signal conditioning technology, a digital interpolating clock recovering technology and a PRML (Partial Response Maximum Likelihood) principle-based maximum likelihood coding technology, high speed data transmission requirements when high-density storage data is read out can be met, meanwhile the intersymbol interference can be well eliminated, and the error rate is reduced.

Methods and apparatus for enhanced timing loop are provided for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). An acquisition timing circuit for generating an acquisition timing signal includes a plurality of compare functions for receiving and comparing consecutive input signal samples on an interleave with a threshold value. The acquisition timing circuit includes a majority rule voting function coupled to the plurality of compare functions for selecting a timing interleave. Tracking timing circuitry for generating a timing error signal during a read operation includes a channel data detector. The channel data detector receives disk signal input samples and includes a multiple-state path memory. The tracking timing circuit includes a low latency detector receiving disk signal input samples. A selector function is coupled to an output of the low latency detector and is coupled to the multiple-state path memory for selecting a state. The selector function utilizes the low latency detector output and selects the state of the path memory. The selector function provides a low latency output corresponding to the selected state. The low latency output is used for generating the timing error signal during a read operation.

The invention provides a part response maximum likelihood (PRML) system having a branch estimating device which comprises, an analog-to-digital converter for receiving an analog input signal, and transforming the analog input signal into digital signal sequence according to the triggering of the sampling clock, a branch estimating device for receiving the digital signal sequence and estimating each of the branch characteristic value, and a Viterbi code converter for receiving the digital signal sequence and the branch characteristic value and decoding the output signal. The PRML system by theinvention can reduce the circuit and raise the speed.

An apparatus for reproducing digital data recorded on a recording medium by a Partial Response Maximum Likelihood method, the digital data being recorded in a code pattern in which the same code continuously appears at least two times, includes an analog-to-digital converting unit that samples an analog reproduction signal recorded on the recording medium and converts the sampled analog reproduction signal into a digital signal; a sampling rate switching unit that adaptively switches the sampling rate in the analog-to-digital converting unit from a higher rate to a lower rate; and a data demodulating unit that reproduces and demodulates the digital signal subjected to the analog-to-digital conversion in the analog-to-digital converting unit by the Partial Response Maximum Likelihood method in accordance with the switching between the higher rate and the lower rate.

A method and apparatus are provided for word synchronization with large coding distance and fault tolerance for a partial-response maximum-likelihood (PRML) data channel in a direct access storage device (DASD). A Viterbi detector receives equalized PR4 samples including a predefined word synchronization pattern. The Viterbi detector is a dedicated detector optimized for detecting the predefined word synchronization pattern. The Viterbi detector includes a two-state Viterbi trellis and a word synchronization detector for the two-state Viterbi trellis. The predefined word synchronization pattern includes only even length magnets. The predefined word synchronization pattern is a repetition code including pairs of ones and pairs of zeros and includes multiple pattern match sequences. The Viterbi detector is optimized with branches removed from the Viterbi trellis, thus increasing coding distance. The two-state Viterbi trellis and word synchronization detector of the Viterbi detector operate on a 2T basis, where 1/T is the sample rate.

A method is provided for optimizing a PRML (Partial Response Maximum Likelihood) receiving channel for mass memory data receiving systems comprising an input receiving channel, a receiver placed downstream of the channel, a detector connected in cascade to the receiver, and a summing node being input both the receiver output through a delay line, and the output from the detector through an impulsive filter. The method includes performing an indirect estimate of the noise strength by filtering out the error sequence, i.e. the output signal from the summing node, through a filter, and selecting either the output from the summing node or the output from the filter to obtain an optimization parameter for feedback to the receiving system.

Compact pulse shape partial response (CPS PR) signaling is developed for trellis based signals like QM-MSK, and for PAM/QAM type signals to improve the performance to bandwidth tradeoff. Compact pulse shaped signals are partial response signals that employ a very short pulse shaping filter and use Viterbi decoding to optimally detect the CPS signal in presence of its inherent inter-symbol interference. The CPS filters considered herein have much shorter impulse response than the well-known raised cosine (RC) filter. There is no need to equalize the received signal to eliminate ISI or to allow a fixed amount of ISI between received signal samples as sampled at the symbol rate as is common in partial response maximum likelihood (PRML) systems. Numerical results indicate that CPS QM-MSK and CPS QAM provides between several dB of gain, depending on constellation size, over PR-CPM and RC QAM, when compared at a given value of bandwidth, i.e., B₉₉T_b.

A decoding circuit has a nonlinear equalizer which employs a signal conditioning algorithm for conditioning a partial response sampled signal to eliminate intersymbol interference. The inventive decoding circuit has an analog-to-digital converter for sampling an analog signal, a linear equalizer for adjusting the amplitude and phase relations of the sampled signal, a nonlinear equalizer for conditioning the sampled signal and outputting a partial response sampled signal having two nonzero samples, and a partial response maximum likelihood detector, for detecting the partial response sampled signal having two nonzero samples.

A decoding method for optical storage device, which decodes channel bits upon a disc by partial response maximum likelihood (PRML) detection, is proposed. Unlike the conventional skills, the present method does not decode the detected RF signals directly, but adjusts values of parts of detected RF signals to their original ideal values before channel decoding instead, thereby reducing the decoding error rate of channel bits. The decoding method includes the step of: retrieving a first sequence of RF signals; identifying if the first sequence of RF signals contains a signal combination which satisfies a particular condition; adjusting a plurality of RF signals in the first sequence of RF signals to some pre-determined RF signals' value and then forming a second sequence of RF signals; and decoding the second sequence of RF signals. In a preferred embodiment of the invention, the method is applied to an optical storage system of PR (1,2,2,2,1) channel.

A partial response maximum likelihood decoder, such as a Viterbi decoder, implements a set of combined states where each combined state can represent at least two states from a plurality of complementary sets of states. For each data symbol and each combined state, a Viterbi processor (703) determines a path metric and a substate indication for each path to the combined state. A path selection processor (709) of the Viterbi processor (703) selects a selected path and a selected sub state indication for the path which corresponds to a highest likelihood path metric. The substate indication is an indication of which of the complementary set of states the combined state represents for the data symbol. The invention allows a substantial complexity reduction and/or reduced computational burden as the Viterbi algorithm can be applied to a reduced number of combined states.