Manufacturing method for cilicon epitaxial wafer for 6'' VDMOS tube

Abstract

The present invention relates to a preparation method of silicon epitaxial wafer for power VDMOS tube. Firstly, selection and usage of substrate are important, the selected substrate not only can meet the requirements for device, but also can meet the requirements for epitaxy. Its preparation method includes the following steps: selecting proper gas corrosion flow and gas corrosion time, reducing concentration of gas corrosion impurity in epitaxial reactor so as to reduce self-doping in epitaxial growth process; first layer epitaxial growth, on the substrate surface with high concentration utilizing lower temperature to grow a layer of purity epitaxial layer, encapsulating substrate surface and edge, controlling its growth temperature, growth rate and epitaxial time so as to make encapsulating layer obtain ideal effect, at the same time, selecting proper epitaxial condition to make the deformation of epitaxial wafer be minimum; and second layer epitaxial growth, utilizing tower temperature to grow a layer of epitaxial layer whose resistivity and thickness can meet requirements for device.

Description

1. Technical field [0001] The present invention relates to a silicon epitaxial wafer, in particular, to a manufacturing method of a silicon epitaxial wafer for 6" VDMOS power tube. 2. Background technology [0002] Power MOSFET is a voltage-controlled unipolar transistor, which controls the drain current through the gate voltage, so one of its notable features is that the driving circuit is simple and the driving power is small; it is only conducted by majority carriers, and there are no minority carriers. Storage effect, good high-frequency characteristics, operating frequency up to 100kHz or more, the highest frequency among all power electronic devices, so it is most suitable for high-frequency applications such as switching power supply, high-frequency induction heating; no secondary breakdown problem, safe work Wide area, strong damage resistance. It adopts the fine processing technology of VLSI and uses N / N+ epitaxial structure, so it has special requirements and stan...

AI Technical Summary

Problems solved by technology

The result is: high resistivity in the center of the epitaxial wafer, low resistivity at the edge, small center and large edge in the transition zone of the epitaxial wafer

When the device is manufactured, the breakdown voltage BVDS is small in the middle and the edge is small, and the on-resistance Rdson is also small in the middle and the edge. This not only reduces the control range of the epitaxial wafer parameters, but also increases the difficulty of parameter control, and also causes the device yield Decline

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