A low-stress LED inversely installed power chip and its preparation
A power chip, low-stress technology, applied in semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, semiconductor devices, etc., can solve the problem of high stress on epitaxial wafers and thermally conductive substrates, decreased device light extraction efficiency, thermal resistance and stress. Large and other problems, to achieve the effect of improving stress and stability problems, optimizing heat dissipation and stability, and reducing thermal resistance and stress
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Embodiment 1
[0026] In order to prepare the aforementioned low-stress LED flip-chip power chip, the preparation method of the present invention includes the following steps:
[0027] First, use MOCVD (metal organic chemical vapor deposition) equipment to epitaxially grow GaN-based high-power LED structure epitaxial wafers, the substrate is sapphire (Al 3 O 2). Then, etch the N-side steps and chip-size scribe lanes to expose the N-GaN mesa for use as N electrodes and solder pads. The N-type mesa is etched with a reactive ion etching equipment RIE, and the reaction gas is Cl:Ar=10:3. Use ICP (coupled ion etching) or RIE (reactive ion etching) equipment to perform dry etching with chloride ions and argon ions to form the P-GaN layer and the light-emitting layer, and make the P-GaN layer and the light-emitting layer below it N-GaN layer to form electrical contact, use photoresist or SiO when etching 2 Make a mask.
[0028] Secondly, a transparent conductive thin film ITO with a thickness of 200nm-...
Embodiment 2
[0031] Adjusting the pad area (Pad area) between the epitaxial wafer with P-N electrodes and the silicon substrate reduces the stress of the chip and optimizes the chip yield. The process parameters for welding the LED wafer and the silicon substrate are as follows:
[0032] The percentage of the pad area between the P-N electrode epitaxial wafer and the substrate is controlled at 50% to 80%. The smaller the percentage of contact area, the higher the yield of the chip. When the contact area percentage increases from 10% to 90%, the chip yield rate drops from 70% to 20%. Chip stability test conditions: current is 350 mA, time is ~1000hrs. When the contact area is small, the chip stability is good. When the P-N electrode epitaxial wafer is partially in contact with the substrate, the chip stress is small and the performance is stable, but the heat dissipation is poor. When the P-N electrode epitaxial wafer is in full contact with the substrate, the chip heat dissipation is good, but...
Embodiment 3
[0034] Adjust the type and thickness of the filling material to optimize the thermal resistance of the chip.
[0035] The filling material for flip-chip welding is pure gold and a combination compound of Au, Al, Cu, Pb, Sn, In, etc. The thickness of the filling material between the P-GaN layer and the reflective layer of the silicon substrate is 2 μm-10 μm. In the case of filling with different thicknesses, the relationship between the contact area (Pad area) and its thermal resistance: when the type and thickness of the filling material are constant, when the contact area is large, the thermal resistance is small; when the type and contact area of the filling material are constant, the filling When the material thickness is large, the thermal resistance is large; when the filling material thickness and contact area are constant, when the thermal conductivity of the filling material is large, the thermal resistance is small.
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Abstract
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