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Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method

A technology of Schottky diodes and MOS devices, which is applied in the manufacture of semiconductor/solid-state devices, electric solid-state devices, semiconductor devices, etc., can solve the problems of high cost, large chip area and complex process, and achieves saving silicon surface area and reducing The effect of chip cost

Active Publication Date: 2010-10-06
SUZHOU SILIKRON SEMICON CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the disadvantages are always: 1. The Schottky diode structure occupies a large amount of silicon surface area, resulting in a large chip area and high cost; 2. An additional mask is required for photolithography, which is complicated in process and high in cost.

Method used

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  • Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method
  • Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method
  • Groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in unit cell and manufacture method

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Experimental program
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Embodiment 1

[0059] Such as image 3 and Figure 4 As shown, the structure of the grooved N-type MOS device integrating Schottky diodes in the unit cell of the present invention is: on the top view plane, the center is a parallel unit cell array area 1, and the periphery of the unit cell array area 1 is provided with a guard ring 2 and Stop ring 3 and other terminal protection structures. An upper metal layer 9 is deposited on the top surface of the unit cell array region 1, and the upper metal layer 9 is metal aluminum, or metal aluminum doped with copper, or metal aluminum doped with copper and silicon. The bottom of the unit cell array region 1 includes a lower metal layer (not shown in the figure), an N+ monocrystalline silicon substrate 10 and an N− epitaxial layer 11 from bottom to top. In the N-epitaxial layer 11, several grooves 4 are provided in parallel in the longitudinal direction and the lateral direction, and the several grooves 4 provided in parallel in the longitudinal di...

Embodiment 2

[0096] Such as Figure 6 As shown, the difference between this embodiment and Embodiment 1 is that the gate oxide layer 22 at the bottom of the trench 4 is thicker, that is, the gate oxide layer 22 at the bottom of the trench 4 is thicker than the gate oxide layer on the sidewall of the trench 4 12 thickness, the other structures are basically the same, and will not be described again here. Thickening the gate oxide layer 22 at the bottom of the trench 4 can bring two advantages: first, the parasitic capacitance between the gate and the drain becomes smaller. The switching power loss in the process of dynamic on and off of the MOSFET device can be reduced. Second, when the MOSFET channel is turned off, due to the large bias voltage at the drain, there will be a strong electric field at the bottom of the trench, and a thicker gate oxide layer 22 can improve the ability of the device to withstand strong electric fields and avoid Device failure due to drain-to-gate breakdown. ...

Embodiment 3

[0103] Such as Figure 8 As shown, the difference between this embodiment and Embodiment 1 is that a polysilicon shielding layer 25 is added at the bottom of the trench 4 , and the polysilicon shielding layer 25 is located under the conductive gate polysilicon 13 in the trench 4 . Other structures are basically the same, and will not be described again here. The benefit of adding the polysilicon shielding layer 25 at the bottom of the trench 4 is mainly to reduce the parasitic capacitance between the gate and the drain. The structure can reduce the switching power loss during the dynamic on and off process of the MOSFET device.

[0104] The manufacturing method adopted for adding the polysilicon shielding layer 25 at the bottom of the trench 4 is: based on the process steps of Embodiment 1, the following steps are added between the ninth step and the tenth step:,

[0105] refer to Figure 9A :

[0106] After the ninth step, the upper surface of the whole structure uniforml...

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Abstract

The invention relates to a groove MOS (Metal Oxide Semiconductor) device integrating Schottky diodes in a unit cell and a manufacture method. In the method, the Schottky diodes are technically integrated in each groove MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) unit cell, and an N+source electrode ohmic contact of the MOSFET, an ohmic contact of a P-shaped well and anode contacts of the Schottky diodes commonly use a same contact hole, thereby efficiently saving the area of the silicon surface and lowering the chip cost. On the aspect of manufacture technology, the invention does not need an additional photomask or a photoetching step, but introduces an easily controlled medium side wall and a self-aligned technology and can also obtain the groove MOSFET device with low cost, simple processing steps, high performance and high reliability.

Description

technical field [0001] The invention relates to a high-power MOS device and a manufacturing method thereof, in particular to a trench MOS device integrating a Schottky diode in a unit cell and a manufacturing method thereof. Background technique [0002] Trench MOSFET devices are widely used in power circuits as switching devices to connect power and loads. For a long time, how to reduce power loss has been the most concerned issue, especially in today's advocacy of energy saving, emission reduction and low carbon. [0003] figure 1 It is a schematic diagram of a DC-DC conversion control circuit using a MOS tube as a switching device. It can be seen from the figure that the trench MOSFET devices M1 (lower tube) and M2 (upper tube) are the core switching devices of the circuit, and the DC-DC conversion is realized through the control chip. Among them, there are parasitic components in M1 and M2. Diodes D1 and D2 (composed of P-type well regions / drains surrounding the sourc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/04H01L23/528H01L21/77
CPCH01L2924/0002
Inventor 刘伟王凡程义川
Owner SUZHOU SILIKRON SEMICON CO LTD
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