Preparing and etching method of plugged-in TiN metal gate lamination structure

Abstract

The invention discloses a preparing and etching method of a plugged-in TiN metal gate lamination structure. The preparing and etching method comprises the following steps: forming an interface SiO2 layer on a semiconductor substrate; forming a high-K gate dielectric layer on the interface SiO2 layer; after the high-K gate dielectric layer is subjected to quick thermal annealing treatment, forminga TiN metal gate electrode layer on the high-K gate dielectric layer; forming a silicon gate layer on the TiN metal gate electrode layer; forming a hard mask layer on the silicon gate layer; photoetching: etching the hard mask layer by the dry etching technology; removing photoresist: taking the hard mask layer as a mask, and carrying out anisotropic etching on the silicon gate layer by the dry etching technology; and carrying out anisotropic etching with a high selection ratio on the TiN metal gate electrode layer and the high-K grid dielectric layer by the dry etching technology. According to the preparing and etching method, the preparation requirements of the TiN metal gate and the high-K material in the plugged-in metal gate lamination structure can be satisfied, and a steep etching section can be obtained by optimizing the etching technology of the TiN metal gate and the high-K medium, thereby providing necessary guarantee for the integration of a high-K / metal gate.

Description

technical field [0001] The invention relates to the technical field of integrated circuit manufacturing, in particular to a method for preparing and etching a metal gate stack structure in a gate-first process. Background technique [0002] As the feature size of semiconductor devices enters the 45nm technology node, in order to reduce the gate tunneling current, reduce the power consumption of the device, and completely eliminate the polysilicon depletion effect and P-type metal-oxide-semiconductor field effect transistor (PMOSFET) Reliability issues caused by medium B penetration, alleviate the Fermi level pinning effect, and use high dielectric constant (K) / metal gate materials instead of traditional SiO 2 / Polysilicon (poly) structure has become an inevitable choice. Among many high-K materials, Hf-based high-K materials are finally considered to be the most promising SiO2 materials. 2 Alternatives to gate dielectrics. On the other hand, TiN metal gate material has b...

AI Technical Summary

Problems solved by technology

[0003] Although the introduction of Hf-based high-K and metal gate materials can improve the performance of the device, the integration of high-K / metal gate in the gate-first process, especially the etching process of the metal gate stack structure, has always been a high-K, metal One of the main challenges in the practical application of gate materials to CMOS processes

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