Copper interconnection structure and manufacturing method thereof
A technology of copper interconnection structure and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve problems affecting product yield, achieve the effect of improving yield and reducing the formation of protrusion defects
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Embodiment 1
[0039] Please refer to image 3 , providing a substrate 33 on which a low-K dielectric layer 31 and copper interconnection lines 32 located in the low-K dielectric layer 31 are formed. Wherein, the substrate 33 may specifically include a silicon substrate, various functional devices, an NDC layer, etc., wherein, for example, the silicon substrate may be monocrystalline silicon, silicon-on-insulator (SOI), etc., and the device may be a CMOS transistor Wait. The low-K dielectric layer 31 includes but not limited to the following materials: silicon oxide doped with boron or carbon, or SiLK produced by Dow Chemical Company.
[0040] In this example, then, using H 2 Perform annealing treatment on the low-K dielectric layer 31 and the copper interconnection 32 located in the low-K dielectric layer 31, wherein H 2 The temperature required for the annealing process is preferably 370-390° C., and the hydrogen purity is preferably greater than 99.9%. The H 2 The purpose of the anne...
Embodiment 2
[0044] The substrate, the low-K dielectric layer and the copper interconnection line used in this embodiment are the same as those in the first embodiment. It must also go through the same annealing treatment, and use the plasma enhanced chemical vapor deposition process (PECVD) with the same process conditions to form the Si-C-B mask layer. Wherein, the process conditions of the plasma enhanced chemical vapor deposition process (PECVD) are: pressure 1-7 torr, electric power 50-1000w, temperature 300-400°C. The difference is that the reaction gases for forming the Si-C-B mask layer are: trimethylsilane (3MS) and B 2 h 6 . In the present embodiment, the flow rate of the reaction gas is: trimethylsilane (3MS) 50~1000 sccm, B 2 h 6 50~1000 sccm. The Si-C-B mask layer is formed by reaction, here, reference can be made accordingly Figure 4 As shown, a Si—C—B mask layer 40 is formed on the low-K dielectric layer 31 and the copper interconnection 32 .
[0045] After the proce...
Embodiment 3
[0047] The substrate, low-K dielectric layer and copper interconnection used in this embodiment are the same as those in Embodiment 1 and Embodiment 2. It must also go through the same annealing treatment, and use the plasma enhanced chemical vapor deposition process (PECVD) with the same process conditions to form the Si-C-B mask layer. Wherein, the process conditions of the plasma enhanced chemical vapor deposition process (PECVD) are: pressure 1-7 torr, electric power 50-1000w, temperature 300-400°C. The difference is that the reaction gases for forming the Si-C-B mask layer are: tetramethylsilane (4MS) and B 2 h 6 . In the present embodiment, the flow rate of reaction gas is: tetramethylsilane (4MS) 50~1000sccm, B 2 h 6 50~1000 sccm. The Si-C-B mask layer is formed by reaction, here, reference can be made accordingly Figure 4 As shown, a Si—C—B mask layer 40 is formed on the low-K dielectric layer 31 and the copper interconnection 32 .
[0048] After the process re...
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Abstract
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