Construction method and circuit of master-slave follower type single-edge k-value flip-flop using circuit three-element theory
A technology with three circuit elements and a construction method, which is applied in the field of construction of a master-slave follower-type single-edge K-value flip-flop, which can solve problems such as large hysteresis voltage, floating gate capacitance leakage cannot be omitted, and control threshold
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Embodiment 1
[0077] Embodiment 1: Utilize the existing formulas (5a) and (5b) of the circuit three-element theory of the circuit three-element theory;
[0078] Binary is similar to multi-valued circuits and analog circuits, the main feature is the three elements of the circuit: signal, network and load; multi-valued signal is the rounding of analog signals within a certain range, when the number of rounding is sufficiently large (quite The number of scales is sufficiently large), and its limit is the analog signal. The focus of digital circuit research should be based on the three elements of "circuit behavior" rather than "logic realization"; it is customary to regard "logic circuit" as the essence of "logical thinking" "Logic implementation", originally "circuit" and "logic" are not equivalent to each other, "circuit" is not the circuit realization of "logic", and "logic" is not an abstraction of "circuit", that is, the two are not equal If the problem is not completely described, it ...
Embodiment 2
[0083] Embodiment 2: The working process of the clock falling edge delay circuit δtcp.
[0084] The clock falling edge delay circuit δtcp is shown as Figure 8 , the circuit works as follows: cp 0 Before the rising edge, the NMOS transistor N d1 cut-off, NOT gate UC d2 output cp 1 is high level; when cp 0 When the rising edge comes, the tube N d1 Rapid conduction (∵ tube N d1 Gate connected to cp 0 ), tube N d1 drain (i.e. capacitor C d1 Potential and NOT gate UC d1 input) quickly falls to low level, the NOT gate UC d1 The output goes high and is sent to the NOT gate UC d2 input, make cp 1 quickly by high level V DC goes low, quickly changes from 0 to V DC , indicating that cp 1 falling edge (i.e. rising edge) and cp 0 The rising edge comes at the same time.
[0085] when cp 0 When the falling edge comes, the tube N d1 Expeditious cutoff due to tube N d1 The drain is connected to a capacitor C d1 , so V DC Through resis...
Embodiment 3
[0090] Embodiment 3: Slave follower AF.
[0091] Slave follower AF (analog follower) as shown Figure 4 ,Will Figure 4 Middle PMOS tube P m1 delete, you get Figure 5 The common NMOS transistor source follower shown (by NMOS transistor N m1 and source resistor R m1 composition), or will Figure 4 Medium source resistance R m1 delete, get Figure 6 The CMOS tube source follower shown (by the NMOS tube N m1 and PMOS transistor P m1 composition). Because the output of the follower is connected to the gate of the next-stage MOS transistor, the gate capacitance of the MOS transistor is a capacitive load for the AF output, so that Figure 6 The shown CMOS tube source follower has a hysteresis phenomenon similar to a Schmidt circuit. The output voltage rise and fall trajectory caused by the input voltage rise and fall is inconsistent, and the hysteresis voltage Δ=V TN +|V TP |(∵The capacitive load has a memory effect, which rises and falls with the input...
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