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Construction method and circuit of master-slave follower type single-edge k-value flip-flop using circuit three-element theory

A technology with three circuit elements and a construction method, which is applied in the field of construction of a master-slave follower-type single-edge K-value flip-flop, which can solve problems such as large hysteresis voltage, floating gate capacitance leakage cannot be omitted, and control threshold

Inactive Publication Date: 2017-05-03
HEILONGJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] With the rapid development of MOS integrated circuit technology, the integration scale is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70℅ of silicon chip area; in programmable logic devices, a large number of programmable internal wiring is also required to connect each logic function block or input / output to complete a circuit with a specific function. Wiring (including programming connection switches) accounts for a large part of the material cost
[0007] 1. In the realization of multi-valued circuits (K≥3), the existing semiconductor manufacturing process control MOS transistor threshold technology has great disadvantages: ① the range of control threshold is limited (because the ion implantation concentration is limited), and the control threshold in the process The amplitude often changes the performance of the MOS tube, and the voltage-type multi-valued circuit thus realized is not larger than the 4-valued circuit, and the application of more-valued circuits is difficult
② Only the amplitude of the threshold can be controlled, and the opening properties of the MOS tube cannot be changed (such as high-pass, low-pass, band-pass, and band-resistance). The simplest circuit structure
③ It is necessary to add an additional process of ion implantation, and the threshold can only be controlled in the semiconductor manufacturing process, which not only increases the complexity of the process, but also cannot be controlled by the user
[0008] 2. In the realization of multi-valued circuits, the existing neuron MOS transistor control threshold technology has great disadvantages: ① With the increase of K value, 'the input gate and control gate capacitance of a single neuron MOS transistor occupies the area of ​​the silicon chip' versus 'a single neuron MOS transistor'. The ratio of the MOS tube to the area of ​​the silicon chip is getting larger and larger, such as ten times, a hundred times or higher; ②As the K value increases, the width of the threshold fuzzy region (turning region) of the input gate ΔV 1 'to' Floating Gate Threshold Fuzzy Area (Turning Area) Width ΔV fg ’ ratio (ΔV 1 / ΔV fg =C TOT / C 1 ) is getting bigger and bigger, because ΔV fg is certain, the threshold fuzzy area ΔV of the input gate 1 The width is getting bigger and bigger, so that the input gate K value signal resolution ability is getting lower and lower, and the capacitance accuracy is high, which is not conducive to or cannot reliably realize the multi-valued circuit with large K value; ③The threshold control characteristics cannot be changed (such as with Pass-through and band-stop control threshold mode), which is unfavorable for simplifying the K value circuit; ④ With the increase of the K value, the ratio (C TOT / C 1 ) becomes larger, the capacitance of the input gate and the control gate increases, and the high-frequency performance decreases rapidly; ⑤ With the increase of the K value, the leakage of the floating gate capacitance cannot be omitted, and it is difficult to refresh the multi-valued information
⑥The static power consumption of the neuron CMOS inverter is 0 only for the binary signal. For a large K value, there is a state where the NMOS tube and the PMOS tube are turned on at the same time, and the static power consumption is even greater; the output of the neuron CMOS follower is usually For capacitive loads, the output voltage rises and falls on different tracks, and there is a large hysteresis voltage, which is not conducive to multi-valued circuits.
[0009] 3. The K-value static trigger circuit has K stable states, which can transition from the original steady state to the new steady state under the action of external signals. Generally, at least two K-value gate circuits are cross-connected to form a DC feedback closed loop. way, so as to maintain a certain steady-state K one; similar to the binary single-edge trigger, the static K-value single-edge trigger only needs to use at least 6 multi-value gate circuits, which is difficult to realize with 2 K-value gate circuits

Method used

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  • Construction method and circuit of master-slave follower type single-edge k-value flip-flop using circuit three-element theory
  • Construction method and circuit of master-slave follower type single-edge k-value flip-flop using circuit three-element theory
  • Construction method and circuit of master-slave follower type single-edge k-value flip-flop using circuit three-element theory

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Experimental program
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Effect test

Embodiment 1

[0077] Embodiment 1: Utilize the existing formulas (5a) and (5b) of the circuit three-element theory of the circuit three-element theory;

[0078] Binary is similar to multi-valued circuits and analog circuits, the main feature is the three elements of the circuit: signal, network and load; multi-valued signal is the rounding of analog signals within a certain range, when the number of rounding is sufficiently large (quite The number of scales is sufficiently large), and its limit is the analog signal. The focus of digital circuit research should be based on the three elements of "circuit behavior" rather than "logic realization"; it is customary to regard "logic circuit" as the essence of "logical thinking" "Logic implementation", originally "circuit" and "logic" are not equivalent to each other, "circuit" is not the circuit realization of "logic", and "logic" is not an abstraction of "circuit", that is, the two are not equal If the problem is not completely described, it ...

Embodiment 2

[0083] Embodiment 2: The working process of the clock falling edge delay circuit δtcp.

[0084] The clock falling edge delay circuit δtcp is shown as Figure 8 , the circuit works as follows: cp 0 Before the rising edge, the NMOS transistor N d1 cut-off, NOT gate UC d2 output cp 1 is high level; when cp 0 When the rising edge comes, the tube N d1 Rapid conduction (∵ tube N d1 Gate connected to cp 0 ), tube N d1 drain (i.e. capacitor C d1 Potential and NOT gate UC d1 input) quickly falls to low level, the NOT gate UC d1 The output goes high and is sent to the NOT gate UC d2 input, make cp 1 quickly by high level V DC goes low, quickly changes from 0 to V DC , indicating that cp 1 falling edge (i.e. rising edge) and cp 0 The rising edge comes at the same time.

[0085] when cp 0 When the falling edge comes, the tube N d1 Expeditious cutoff due to tube N d1 The drain is connected to a capacitor C d1 , so V DC Through resis...

Embodiment 3

[0090] Embodiment 3: Slave follower AF.

[0091] Slave follower AF (analog follower) as shown Figure 4 ,Will Figure 4 Middle PMOS tube P m1 delete, you get Figure 5 The common NMOS transistor source follower shown (by NMOS transistor N m1 and source resistor R m1 composition), or will Figure 4 Medium source resistance R m1 delete, get Figure 6 The CMOS tube source follower shown (by the NMOS tube N m1 and PMOS transistor P m1 composition). Because the output of the follower is connected to the gate of the next-stage MOS transistor, the gate capacitance of the MOS transistor is a capacitive load for the AF output, so that Figure 6 The shown CMOS tube source follower has a hysteresis phenomenon similar to a Schmidt circuit. The output voltage rise and fall trajectory caused by the input voltage rise and fall is inconsistent, and the hysteresis voltage Δ=V TN +|V TP |(∵The capacitive load has a memory effect, which rises and falls with the input...

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Abstract

The invention discloses a master-slave follower type single-edge K value trigger constructing method utilizing the circuit three-element theory and a master-slave follower type single-edge K value trigger circuit. The master-slave follower type single-edge K value trigger composed of a digital follower and an analog follower is obtained by means of the circuit three-element theory, a distinctive three-beat work mode is adopted, clock falling edge triggering is adopted, an identical simplest element level circuit structure is obtained under eight optimum coding, due to the fact that a slave follower is an NMOS tube source electrode follower, only the structure scale of a main follower becomes large along with the increase of the K value which is equal to 4,5,6..., other circuit structures do not change, the main follower is the digital follower composed of a high-pass variable-threshold PMOS tube, the output logic level clamp function is realized, and the anti-jamming capability is high. The master-slave follower type single-edge K value trigger circuit is simple in structure, can serve as a K value static storage cell of a K value SSRAM, and can be used in the VLSI field such as FPGA, CPLD, semi-custom or full-custom ASIC and storer and other digital IC technical fields.

Description

[0001] (1) Technical field [0002] The invention belongs to the field of digital integrated circuits, and in particular relates to a construction method and circuit of a master-slave follower type single-edge K-value trigger utilizing the circuit three-element theory. [0003] (2) Background technology [0004] With the rapid development of MOS integrated circuit technology, the scale of integration is getting larger and higher, and VLSI (Very Large Scale Integration) has some shortcomings: ① First, on the VLSI substrate, the wiring takes up more than 70℅ of silicon In programmable logic devices, a large number of programmable internal wiring is also required to connect each logic function block or input / output to complete a circuit with a specific function. Wiring (including programming connection switches) accounts for a large part of the material. cost. Reducing the proportion of wiring costs becomes a very important issue. ② From the perspective of information transmissi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/3562
Inventor 方振贤刘莹方倩
Owner HEILONGJIANG UNIV