Semiconductor device based on double patterns and manufacturing method thereof and electronic device

A semiconductor and double-patterning technology, which is applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as performance degradation and affecting the performance of semiconductor devices, and achieve good uniformity and consistency, good uniformity and consistency , the effect of good craftsmanship

Active Publication Date: 2016-04-06
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] Among them, the spacer is widely used in self-aligned double patterning (Self-aligned double patterning, SADP), usually using lithography-etch-film deposition-etch-removal-nucleus-etch (Litho–Etch–filmdeposition-Etch–Strip -Etch.) method to prepare a semiconductor device, such as selecting a photoresist and patterning it as a core (core) in a double pattern, t

Method used

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  • Semiconductor device based on double patterns and manufacturing method thereof and electronic device
  • Semiconductor device based on double patterns and manufacturing method thereof and electronic device
  • Semiconductor device based on double patterns and manufacturing method thereof and electronic device

Examples

Experimental program
Comparison scheme
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Example Embodiment

[0075] Example 1

[0076] Attached below Figure 2a -2K further illustrates the method of the present invention, where Figure 2a -2K is a schematic diagram of a process of manufacturing a semiconductor device based on a dual pattern method in an embodiment of the present invention.

[0077] First, step 201 is performed to provide a semiconductor substrate 201, on which a dummy pattern material layer 203, a hard mask material layer 204, and a patterned mask layer 205 are formed.

[0078] Specifically, such as Figure 2a As shown, the semiconductor substrate 201 may be at least one of the materials mentioned below: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI) ), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI), etc.

[0079] Optionally, an isolation structure may also be formed in the semiconductor substrate, and the isolation structure is a shallow trench isolation (STI) structure or a localized si...

Example Embodiment

[0133] Example 2

[0134] The present invention also provides another semiconductor preparation situation, such as Figure 3a-3b As shown, the distance between the first spacer is M, and the distance between the second spacer is N. In this embodiment, the M﹥N, such as Figure 3a Shown.

[0135] Then the size of the second spacer is etched back to reduce the size of the second spacer, so that the distance between the spacer arrays is equal

[0136] In this step, first measure the distance between the first gap wall and the distance between the second gap wall, and then use wet peeling or etching trimming to reduce the first gap wall or the second gap. The size of the gap wall.

[0137] The rest of the preparation steps can refer to Example 1, which will not be repeated here.

Example Embodiment

[0138] Example 3

[0139] The present invention also provides a semiconductor device, which is prepared by using the method described in Embodiment 1 or 2. The pattern of the semiconductor device prepared by the method of the present invention has good uniformity and consistency, so as to further improve the performance and yield of the semiconductor device.

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Abstract

The invention relates to a semiconductor device based on double patterns and a manufacturing method thereof and an electronic device. The method comprises the steps that step S1: a semiconductor substrate is provided, and multiple virtual nuclear lamination layers which are arranged in a spacing way are formed on the semiconductor substrate; step S2: square first clearance walls and second clearance walls are formed on the sidewalls of the virtual nuclear lamination layers in turn; step S3: the virtual nuclear lamination layers are removed so that clearance wall arrays formed by the first clearance walls and the second clearance walls are obtained; and step S4: the first clearance walls or the second clearance walls are back etched so that distance between the clearance wall arrays is enabled to be equal. Advantages of the semiconductor device based on the double patterns and the manufacturing method thereof and the electronic device are that (1) the method has better process window and process margin for an SADP technology; (2) homogeneity and consistency of the key size of the patterns can be better controlled; (3) the distance between the clearance wall array patterns is equal; and (4) clearance wall array patterns have great homogeneity and consistency so that final patterns can be greatly controlled, and the final patterns are enabled to have great homogeneity and consistency.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular, the invention relates to a semiconductor device based on a double pattern, a manufacturing method thereof, and an electronic device. Background technique [0002] With the increasing demand for high-capacity semiconductor storage devices, the integration density of semiconductor storage devices has attracted people's attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art. The continuous shrinkage of the device, the double-patterning technology (Double-Patterning, DP) is being widely accepted and applied as a solution in the device preparation process. [0003] Double-patterning (DP) technology overcomes the K1 limitation through pitch fragmentation, and thus is widely used in the preparation of semiconductor devices. At present, in Double-Patterning (DP) technology, there are sel...

Claims

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Application Information

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IPC IPC(8): H01L21/027H01L21/3105G03F7/16
Inventor 王新鹏
Owner SEMICON MFG INT (SHANGHAI) CORP
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