Semiconductor device based on double patterns and manufacturing method thereof and electronic device

Abstract

The invention relates to a semiconductor device based on double patterns and a manufacturing method thereof and an electronic device. The method comprises the steps that step S1: a semiconductor substrate is provided, and multiple virtual nuclear lamination layers which are arranged in a spacing way are formed on the semiconductor substrate; step S2: square first clearance walls and second clearance walls are formed on the sidewalls of the virtual nuclear lamination layers in turn; step S3: the virtual nuclear lamination layers are removed so that clearance wall arrays formed by the first clearance walls and the second clearance walls are obtained; and step S4: the first clearance walls or the second clearance walls are back etched so that distance between the clearance wall arrays is enabled to be equal. Advantages of the semiconductor device based on the double patterns and the manufacturing method thereof and the electronic device are that (1) the method has better process window and process margin for an SADP technology; (2) homogeneity and consistency of the key size of the patterns can be better controlled; (3) the distance between the clearance wall array patterns is equal; and (4) clearance wall array patterns have great homogeneity and consistency so that final patterns can be greatly controlled, and the final patterns are enabled to have great homogeneity and consistency.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular, the invention relates to a semiconductor device based on a double pattern, a manufacturing method thereof, and an electronic device. Background technique [0002] With the increasing demand for high-capacity semiconductor storage devices, the integration density of semiconductor storage devices has attracted people's attention. In order to increase the integration density of semiconductor storage devices, many different methods have been adopted in the prior art. The continuous shrinkage of the device, the double-patterning technology (Double-Patterning, DP) is being widely accepted and applied as a solution in the device preparation process. [0003] Double-patterning (DP) technology overcomes the K1 limitation through pitch fragmentation, and thus is widely used in the preparation of semiconductor devices. At present, in Double-Patterning (DP) technology, there are sel...

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Problems solved by technology

[0005] Among them, the spacer is widely used in self-aligned double patterning (Self-aligned double patterning, SADP), usually using lithography-etch-film deposition-etch-removal-nucleus-etch (Litho–Etch–filmdeposition-Etch–Strip -Etch.) method to prepare a semiconductor device, such as selecting a photoresist and patterning it as a core (core) in a double pattern, then selecting a low-temperature deposition method to form a spacer layer on the photoresist core, and finally removing all The photoresist core is described above, but the deposition and etching process of the spacer at present reduces the performance of the line width roughness (linewidththroughness, LWR), thereby affecting the performance of the semiconductor device

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