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Fabrication method of wafer-level uniaxial strain GE on Aln buried insulating layer based on amorphization and scale effect

An on-insulating, uniaxial strain technology, applied in the field of microelectronics, can solve problems such as excessive mechanical bending, poor compatibility, wafer fragmentation, etc., to avoid breakage and defect problems, high yield, smoothness high degree of effect

Active Publication Date: 2018-08-24
XIDIAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] This method has the following disadvantages: 1) Poor compatibility with traditional integrated circuit technology: in order to obtain Ge wafers on AlN buried insulating layers with different strains, it needs to additionally manufacture corresponding bending stages with different radii of curvature, and the produced The bending table needs to be compatible with existing annealing equipment
2) Poor reliability: This process requires the use of pressure rods to apply mechanical external force to bend the Ge wafer on the AlN buried insulating layer, which will introduce defects in the top layer of germanium; if the Ge wafer on the AlN buried insulating layer is too curved, chipping
3) Due to the fear of breaking the Ge wafer on the AlN buried insulating layer, the bending degree of the mechanical bending cannot be too large, which limits the amount of strain introduced in the top layer of germanium, and the amount of strain that can be achieved is small

Method used

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  • Fabrication method of wafer-level uniaxial strain GE on Aln buried insulating layer based on amorphization and scale effect
  • Fabrication method of wafer-level uniaxial strain GE on Aln buried insulating layer based on amorphization and scale effect
  • Fabrication method of wafer-level uniaxial strain GE on Aln buried insulating layer based on amorphization and scale effect

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Effect test

Embodiment 1

[0044] Embodiment 1, making a wafer-level uniaxial tensile-strained Ge material on a 5-inch AlN buried insulating layer.

[0045] Step 1: Select a 5-inch AlN-buried Ge-on-insulator wafer and clean it.

[0046] (1a) Use acetone and isopropanol to alternately perform ultrasonic cleaning on the Ge wafer on the selected AlN buried insulating layer to remove organic contamination on the substrate surface;

[0047] (1b) Mix ammonia water, hydrogen peroxide, and deionized water in a ratio of 1:1:3 to form a mixed solution, and heat it to 120°C, soak the Ge wafer on the AlN-buried insulating layer in the mixed solution for 12 minutes, and take it out Then rinse with a large amount of deionized water to remove inorganic pollutants on the surface of the Ge wafer on the AlN buried insulating layer;

[0048] (1c) Soak the Ge wafer on the AlN buried insulating layer with HF acid buffer for 2 minutes to remove the oxide layer on the surface.

[0049] Step 2: Deposit SiO 2 Layer 4, such a...

Embodiment 2

[0076] Example 2, manufacturing a wafer-level uniaxial tensile-strained Ge material on a 6-inch AlN buried insulating layer.

[0077] Step 1: Select a 6-inch Ge-on-AlN buried insulating layer wafer and clean it.

[0078] The implementation of this step is the same as step 1 of Embodiment 1.

[0079] Step 2: Take out the Ge wafer on the AlN buried insulating layer after cleaning, and deposit SiO on the top Ge layer 1 by plasma enhanced chemical vapor deposition PECVD process 2 layer, that is, the SiH 4 The flow rate is 45sccm, N 2 O flow is 164sccm, N 2 The flow rate is 800sccm, the gas pressure is 600mTorr, the power is 60W, and the deposition temperature is 300°C, and the SiO with a thickness of 8nm is deposited. 2 Layer 4, such as figure 2 (b) shown.

[0080] Step 3: Use an ion implanter to implant a dose of 2E16cm into the top Ge layer 1 -2 , with an energy of 90keV, C ions to form an amorphized layer 5 inside the top Ge layer 1, such as figure 2 (c) shown.

[00...

Embodiment 3

[0091] Embodiment 3, manufacturing a wafer-level uniaxial compressively strained Ge material on a 16-inch AlN buried insulating layer.

[0092] Step A: Select a 16-inch AlN-buried Ge-on-insulator wafer and clean it.

[0093] The implementation of this step is the same as step 1 of Embodiment 1.

[0094] Step B: Deposit SiO 2 Layer 4, such as figure 2 (b) shown.

[0095] Take out the cleaned Ge wafer on the AlN buried insulating layer, and deposit SiO with a thickness of 9 nm on the top Ge layer 1 by plasma-enhanced chemical vapor deposition PECVD process. 2 Layer 4, such as figure 2 (b) shown.

[0096] The deposition process is as follows: SiH 4 The flow rate is 45sccm, N 2 O flow is 164sccm, N 2 The flow rate is 800 sccm, the gas pressure is 600 mTorr, the power is 60 W, and the deposition temperature is 300° C.

[0097] Step C: forming an amorphized layer 5, such as figure 2 (c) shown.

[0098] Form SiO 2 After the layer 4, Ge ion implantation is carried out t...

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Abstract

The invention discloses a manufacturing method for an AlN buried insulating layer wafer level uniaxial strain Ge based on non-crystallization and the scale effect. The realization steps are that a SiO2 layer is deposited on a cleaned AlN buried Ge-on-insulator wafer top Ge layer; ion injection is performed on the top Ge layer so that as amorphous layer is formed, and the SiO2 layer on the amorphous layer is removed; a tensile stress SiN membrane or a pressure stress SiN membrane is deposited on the top Ge layer and then the SiN membrane is etched into uniaxial tensile stress SiN strip arrays or uniaxial pressure stress SiN strip arrays, and annealing is performed on the wafer so that the amorphous layer is enabled to be recrystallized and the AlN buried insulating layer is enabled to plastically deform; and the SiN strip arrays are etched so that AlN buried insulating layer wafer level uniaxial strain Ge is obtained. The manufacturing method has great heat radiation and high strain amount and can be used for manufacturing the AlN buried insulating layer wafer level uniaxial strain Ge material.

Description

technical field [0001] The invention belongs to the field of microelectronics technology, and relates to semiconductor material manufacturing technology, in particular to a method for manufacturing wafer-level uniaxially strained Ge on an AlN buried insulating layer, which can be used for manufacturing high temperature, high power consumption, high power semiconductor devices and integration High-performance GeOI wafers required for circuits. Background technique [0002] The carrier mobility of traditional bulk Si materials is difficult to meet the needs of future high-performance semiconductor devices and circuits. [0003] The electron and hole mobility of the semiconductor Ge are 2.8 times and 4.2 times that of Si, respectively, and its hole mobility is the highest among all semiconductors. Ge is also an excellent optoelectronic material, and has a wide range of applications in visible light to near-infrared detectors, modulators, optical waveguides, optical emitters, a...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/762H01L21/265H01L21/205H01L21/324C23C16/44
CPCC23C16/44H01L21/265H01L21/324H01L21/762H01L21/7624
Inventor 郝跃戴显英梁彬苗东铭祁林林焦帅
Owner XIDIAN UNIV