Method of preparing ESD device, and ESD device

A technology of ESD devices and epitaxial layers, which is applied in the manufacture of electric solid-state devices, semiconductor devices, semiconductor/solid-state devices, etc., can solve the effect of reducing the leakage induction barrier, increase the leakage current of device leakage junction capacitance, and reduce the performance of semiconductor devices, etc. question

Active Publication Date: 2016-10-05
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] With the continuous development of semiconductor technology, the size of MOSFET is being greatly reduced, but due to the limitation of gate oxide layer thickness and power supply voltage, it is difficult to effectively suppress the short-channel effect (short-channel effect, referred to as SCE) of the device.
[0003] At present, the ultra-shallow junctions (USJ) process is generally used to improve the SCE of ESD (Electro-Static discharge, electrostatic discharge) devices, but it will significantly increase the drain junction capacitance of the device. ) and leakage current (junction leakage), especially in the NMOS device (NMOS with two-step S/D implantation) prepared by the two-step S/D implantation process, due to the high supply voltage (supply voltage), the drain terminal The ion implantation region o

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  • Method of preparing ESD device, and ESD device
  • Method of preparing ESD device, and ESD device
  • Method of preparing ESD device, and ESD device

Examples

Experimental program
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Example Embodiment

[0040] Example one

[0041] Figure 1~5 It is a schematic diagram of the flow structure of the method for preparing an ESD device in Embodiment 1 of the present application; Figure 1~5 As shown, this embodiment is based on the traditional preparation of MOS devices based on the preparation process of ESD devices, specifically:

[0042] Such as figure 1 As shown, a silicon substrate 11 prepared with a well region is provided, and a gate stack structure 13 (gate stack after well) is prepared on the silicon substrate 11; the gate stack structure 13 may be prepared based on a conventional MOS device The high-k metal gate structure (HKMG) prepared by the process includes a gate oxide layer 131, a metal gate 132, a low-resistance layer 133 and sidewall spacers 134, and the gate oxide layer 131 covers a part of the upper surface of the silicon substrate 11. The gate 132 covers the upper surface of the gate oxide layer 131, the low resistance layer 133 covers the upper surface of the metal...

Example Embodiment

[0050] Example two

[0051] Image 6 It is a schematic diagram of the structure of the ESD device in the second embodiment of the present application; the ESD device in this embodiment can be formed on the basis of the method for preparing the ESD device in the above embodiment 1, specifically:

[0052] Such as figure 2 As shown, on the silicon substrate 21 forming the active / drain regions 211, a gate stack structure 22 is provided. The gate stack structure 22 may be a high-k metal gate structure (HKMG) prepared based on a traditional MOS device manufacturing process. ), which specifically includes a gate oxide layer 221, a metal gate 222, a low-resistance layer 223, and sidewall spacers 224, and the gate oxide layer 221 covers part of the upper surface of the silicon substrate 21, and the metal gate 222 covers the upper surface of the gate oxide layer 221 On the surface, the low-resistance layer 223 covers the upper surface of the metal gate 222, and the sidewall spacer 224 is lo...

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Abstract

The invention relates to the technical field of semiconductor manufacturing, and specifically relates to a method of preparing an ESD (Electro-Static Discharge) device and an ESD device. The method of preparing an ESD device comprises the steps: based on a traditional method of preparing an MOS device (such as a PMOS or EMOS device), implanting ESD ions into a mask to open a dielectric layer above a source/drain area; utilizing a wet etching process to form a wide-top and narrow-bottom V type groove in a silicon substrate; and generating two epitaxial layers with different ion doping concentration in the V type groove continuously to form a triangular epitaxial stress layer (namely, a bottom epitaxial layer) in the source/drain area so as to realize the aim of enhancing the channel surface stress and optimizing the ESD trigger voltage on the premise of not performing the ESD ion implantation process and to greatly improve the performance of the ESD device while the device SEC (Short-Channel Effect) can be effectively improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for preparing an ESD device and an ESD device. Background technique [0002] With the continuous development of semiconductor technology, the size of MOSFET is being greatly reduced, but due to the limitation of gate oxide layer thickness and power supply voltage, it is difficult to effectively suppress the short-channel effect (short-channel effect, referred to as SCE) of the device. [0003] At present, the ultra-shallow junctions (USJ) process is generally used to improve the SCE of ESD (Electro-Static discharge, electrostatic discharge) devices, but it will significantly increase the drain junction capacitance of the device. ) and leakage current (junction leakage), especially in the NMOS device (NMOS with two-step S / D implantation) prepared by the two-step S / D implantation process, due to the high supply voltage (supply voltage), the drain termin...

Claims

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Application Information

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IPC IPC(8): H01L21/77H01L27/02H01L21/265
Inventor 赵猛
Owner SEMICON MFG INT (SHANGHAI) CORP
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