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Calibration method for heat processing unit

A correction method, correction value technology, applied in the field of microelectronics and microtechnology, which can solve the problems of approximation, failure to take into account the heating zone, the impact of the output of the operation, etc.

Active Publication Date: 2016-11-23
SOITEC SA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Today, some demanding microelectronics processes cannot tolerate a degree of approximation to the obtained results because of the large impact on operational yield
[0012] Plus, the craft doesn't work perfectly
In fact, it does not take into account the fact that the heating zones are not independent of each other

Method used

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  • Calibration method for heat processing unit
  • Calibration method for heat processing unit
  • Calibration method for heat processing unit

Examples

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example 1

[0090] Common processing treatments applied to SOI substrates include smoothing annealing, which involves exposing the upper layer of silicon to a neutral or reducing atmosphere at elevated temperatures (typically above 1100°C). The treatment makes it possible, among other things, to reduce the roughness of layers exposed to high temperature atmospheres by surface reconstruction.

[0091]The treatment also changes the properties of the underlying dielectric layer, such as its thickness, by virtue of the oxide decomposition effect. This phenomenon is specifically reported in the document "Novel trends in SOI Technology for CMOS applications" by O. Kononchuck et al. This document actually explains that under a high temperature neutral or reducing processing atmosphere, the oxygen atoms of the dielectric layer tend to diffuse through the upper layer and react with its surface, producing volatile particles that are evacuated through the furnace atmosphere.

[0092] An important p...

example 2

[0103] Another common type of thermal treatment in the silicon and SOI field is thermal oxidation. For the manufacture of SOI substrates, especially by the Smart Cut process, a thermal oxide layer is typically grown on at least one of the substrates to be assembled. This oxide layer will constitute the buried oxide layer of the final SOI structure.

[0104] The oxide thickness is measured at multiple points (eg, 40 points) of the processed substrate. From these measurements an average is derived which corresponds to the properties of the substrate monitored for the process. It generally has to be between the control limits defined for the process according to the + / -3sigma rule.

[0105] In the type of thermal processing unit considered for this process, the number of substrate positions is 150 and the number of heating zones is 5.

[0106] The sensitivity model was generated based on 25 measurement locations regularly distributed along the reactors of the entire furnace an...

example 3

[0113] The correction method can also be applied to single wafer thermal processing units, such as RTA (rapid thermal annealing) or RTP (rapid thermal processing) units, which enable, for example, a surface smoothing process at very high temperatures in a very short time. In this case, the reactor is not a large-sized tube, but a chamber capable of accommodating a single wafer. The uniformity of heating does not become trivial because the processes performed in these units are performed at very high temperatures, with very fast temperature rises: if the temperature at the substrate is not controlled, the same The fast reaction kinetics can create a large amount of inhomogeneity. The heating element consists of a halogen lamp.

[0114] The verified substrate properties are the substrate roughness measured by DRM (Differential Reflectance Microscopy), a technique based on the correlation of the optical reflectivity of a layer with its thickness, as explained in document WO2014 / ...

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Abstract

A calibration method for determining temperature set point corrections to be applied to the nominal temperature set points of each of the N heating zones of a heat treatment unit having L substrate locations, includes the following steps: establishing a sensitivity model linking variations of a substrate characteristic at each of M representative locations of the L locations to temperature set point variations applied in each of the N heating zones, the variations respectively reflecting differences with respect to a target characteristic and with respect to the nominal set points; executing the process in the heat treatment unit and on the basis of nominal set points; measuring the substrate characteristic at least at a representative measurement location of each heating zone of the unit to supply M measurements; and determining temperature set point corrections from the sensitivity model, the measurements and the target substrate characteristic.

Description

technical field [0001] The present invention relates to the field of microelectronics and microtechnology. [0002] More specifically, the present invention relates to thermal processing processes, especially applied to thermal processing of silicon or SOI (silicon-on-insulator) wafers. Background technique [0003] Microelectronic thermal processing methods capable of fabricating various layers (eg, silicon oxide layers) or surface treating substrates impose increasingly stringent uniformity parameters. [0004] In fact, the evolution of microelectronics has meant a reduction in the feature size of components with the aim of increasing integration density and circuit speed; in parallel with this, the diameter of silicon and / or SOI wafers is increasing, from 200mm to 300mm or even 450mm, the purpose is to make more dies per wafer. Therefore, there is a need to obtain thinner layers with a more controlled and uniform thickness over a larger area. [0005] The thermal treat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/324
CPCH01L21/324H01L27/1266H01L21/67248H01L27/1203H01L21/67098H01L22/12H01L21/762H01L21/67207H01L27/1229H01L21/7624H01L22/20H01L21/76254
Inventor S·穆热尔D·马斯兰
Owner SOITEC SA
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