Convex block packaging method, semiconductor device and electronic device
A packaging method and semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as photoresist collapse, short circuit of metal lines, and device reliability affecting process stability, etc. Problems, to achieve the effect of improving process stability and device yield, improving adhesion, reducing the risk of photoresist peeling and process defects
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[0029] Combine below figure 2 The bump packaging method of the present invention will be described in detail.
[0030] Such as figure 2 As shown, first, step S201 is performed to provide a semiconductor substrate, and a copper seed layer is formed on the semiconductor substrate.
[0031] The substrate may be at least one of the following materials: silicon, germanium, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium on insulator (S-SiGeOI), insulator Silicon germanium on silicon (SiGeOI) and germanium on insulator (GeOI). In addition, other devices such as PMOS and NMOS transistors may be formed on the semiconductor substrate. An isolation structure may be formed in the semiconductor substrate, and the isolation structure is a shallow trench isolation (STI) structure or a local silicon oxide (LOCOS) isolation structure. CMOS devices may also be formed in the semiconductor substrate, and the CMOS devices are, for example, transistors (for example, NMOS ...
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