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Structural design of high-power planar gate D-MOSFET

A structural design, planar gate technology, applied in electrical components, circuits, semiconductor devices, etc., can solve problems such as reducing the maximum electric field strength, reduce the maximum electric field strength, improve the wafer utilization rate, increase the available on-current density and Effects of inrush current performance

Pending Publication Date: 2017-06-20
SHENZHEN BASIC SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] In order to solve the problem of reducing the maximum electric field intensity in the P-well or N-well corner region under the same blocking voltage without affecting the conduction performance of the D-MOSFET, the present invention provides a high-power planar gate D-MOSFET structure design

Method used

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  • Structural design of high-power planar gate D-MOSFET
  • Structural design of high-power planar gate D-MOSFET
  • Structural design of high-power planar gate D-MOSFET

Examples

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Embodiment 1

[0033] Such as figure 1 Shown is the D-MOSFET structure in the prior art. In this example, figure 1 The planar gate D-MOSFET shown is N-MOS structure, in which 1-P-well, 2-P-well corner region, 3-N+ source region, 4-source level, 5-gate level, 6-insulation layer, 7 -N-drift region, 8-drain stage. When D-MOSFET devices are blocking high voltage, such as figure 1 The P-N junction formed by the shown N-drift region / P-well is reverse biased, and a very high-intensity electric field is generated near the N-drift region / P-well interface. This electric field increases in the area where the curvature of the P-N junction interface is large, and the maximum intensity electric field appears in the P-well corner region 2 of the N-drift region / P-well interface in the D-MOSFET.

[0034] In the widely used wide bandgap material D-MOSFET design at present, the P-well 1 region is implanted with ions through a single mask. Due to the limited diffusion rate of the dopant atoms used in the w...

Embodiment 2

[0047] Such as Figure 4 Shown is a schematic diagram of the structural design of a high-power planar gate D-MOSFET. The corner area is a ladder structure composed of three arcs, but the angle 10 of each batch of ion implantation can be adjusted to produce small sub-steps with different corner curvatures. Each sub-step can use its own independent corner curvature. A small sub-step with a smaller curvature or a larger corner radius can be placed in the deepest part of the P-well as the first corner to further reduce the maximum electric field intensity at the P-well / N-drift region interface, as shown in the figure The radian radius of the bottom sub-step is 1.5 times that of the remaining two steps.

[0048] In a modified embodiment of this embodiment, the arc radius of the lowest sub-step may be any multiple of the remaining steps.

Embodiment 3

[0050] Such as Figure 5 Shown is a schematic diagram of the structural design of the high-power planar gate D-MOSFET. Small sub-steps with different spatial distribution can be produced by adjusting the basic energy of each ion implantation batch, the angle 10 during ion implantation, and the width of the ion implantation window of the corresponding mask, that is, each sub-step can use its own independent depth and width. figure 2 Shown is a linear spatial distribution, non-linear distributions, such as arc-shaped distributions, can be produced by the aforementioned methods. Such as Figure 5 As shown, there is an incremental area generated by a circular arc distribution in the step of the corner area, and the hatched area is the incremental groove grid area formed after the convex circular arc distribution is formed. The curvature of the equivalent P-well / N-drift region interface can be reduced by adopting a circular arc or curved distribution, thereby reducing the maxim...

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Abstract

The invention provides a structural design of a high-power planar gate D-MOSFET, wherein the planar gate D-MOSFET is of an N-MOS structure or a P-MOS structure. The structural design is characterized in that a P-well structure corner region of the N-MOS structure is a step-shaped structure formed by sub-steps, and an N-well structure corner region of the P-MOS structure is a step-shaped structure formed by sub-steps. The step-shaped structure reduces the equivalent interface curvature of the P-well structure corner region and the N-well structure corner region, so that the maximum electric field intensity of the regions is reduced, the possibility of avalanche breakdown inside the D-MOSFET is reduced, the reliability of the D-MOSFET is improved, and the overall availability of the D-MOSFET is improved.

Description

technical field [0001] The invention belongs to the technical field of high-power semiconductors, and in particular relates to a structure design for high-power planar gate D-MOSFETs made of wide-bandgap materials. Background technique [0002] New wide-bandgap semiconductor materials such as silicon carbide and gallium nitride can greatly improve the performance of semiconductor devices, but at the same time, they also bring many challenges in device design and process. Wide bandgap material MOSFET (such as silicon carbide MOSFET) is a high-performance high-power controllable switching power semiconductor device, which has small leakage current in the off state, low conduction loss in the on state, fast switching speed, high operating frequency, High maximum operating temperature and other advantages. The use of wide-bandgap material MOSFET can increase the switching frequency of the inverter, reduce the overall loss, and reduce the demand for energy storage components suc...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06H01L29/78H01L29/423H01L21/336
CPCH01L29/0603H01L29/0684H01L29/423H01L29/66477H01L29/7801
Inventor 张学强张振中和巍巍汪之涵
Owner SHENZHEN BASIC SEMICON LTD
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