PiN diode based on transverse multi-channel structure and preparation method thereof
A multi-channel, diode technology, used in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as performance degradation in the plasma region, limitations in the application of PiN diodes, uneven carrier distribution, etc., to improve The effect of device performance, simple structure and uniform carrier distribution
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Embodiment 1
[0051] See figure 1 , figure 1 A flow chart of a manufacturing method of a PiN diode with a lateral multi-channel structure provided by an embodiment of the present invention includes:
[0052] (a) Select substrate material;
[0053] (b) Etching the substrate to form the first trench region and the second trench region of the multilayer trenches respectively;
[0054] (c) P-type Si is deposited in the first trench region to form a P region;
[0055] (d) Depositing N-type Si in the second trench area to form an N area;
[0056] (e) Lithography leads to complete the fabrication of PiN diodes.
[0057] Further, step (b) may include:
[0058] (b1) Depositing a SiN layer on the surface of the substrate using a CVD process;
[0059] (b2) Using a photolithography process, a first groove area pattern and a second groove area pattern are respectively formed on the surface of the SiN layer;
[0060] (b3) Using a dry etching process to etch the SiN layer and the substrate to form the first trench regi...
Embodiment 2
[0086] Please refer to Figure 2a-Figure 2r , Figure 2a-Figure 2r It is a schematic diagram of a manufacturing process of a PiN diode with a lateral multi-channel structure according to an embodiment of the present invention. The manufacturing method includes the following steps:
[0087] S10. Select an SOI substrate.
[0088] See Figure 2a , The doping type of the SOI substrate 201 is P type, and the doping concentration is 10 14 cm -3 , The crystal orientation is (100); the thickness of the top Si of the SOI substrate 201 is 100 μm.
[0089] S20, depositing a layer of SiN on the surface of the SOI substrate.
[0090] See Figure 2b , Using a CVD process, a SiN layer 202 is deposited on the SOI substrate 201.
[0091] S30, etching the SOI substrate to form a trench in the active area.
[0092] See Figure 2c A photolithography process is used to form an active area pattern on the SiN layer 202, and a dry etching process is used to etch the SiN layer 202 and the top Si at a designated ...
Embodiment 3
[0128] Please refer to image 3 , image 3 It is a schematic structural diagram of a PiN diode with a lateral multi-channel structure provided by an embodiment of the present invention. The solid-state plasma PIN diode is manufactured by the manufacturing method shown in the above-mentioned embodiment. Specifically, the solid-state plasma PIN diode is fabricated and formed on an SOI substrate 301, and the P region 301, N region 302 of the first channel of the PIN diode, P region 303, N region 304 and the third channel of the second channel The P region 305, the N region 306 and the I region laterally located between the P region and the N region are all located in the top Si3011 of the SOI substrate.
[0129] The PiN diode provided in this embodiment prepares a multi-layer channel on an SOI substrate. When a forward voltage is applied to the contact electrode, the superposition of high-concentration carriers in the multiple channels makes the entire intrinsic region carry The ca...
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