Transient voltage suppressor and manufacturing method thereof
A technology of transient voltage suppression and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, circuits, etc., can solve the problems of low chip integration, low ESD resistance, large main device, etc., to improve stability , The effect of chip area reduction and yield improvement
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[0028] Further description will be given below in conjunction with the accompanying drawings and embodiments.
[0029] Step S101: sequentially forming a stacked N+-type single crystal silicon substrate, an N-type silicon epitaxial layer, a buffer oxide layer and a silicon nitride layer. like figure 2 As shown, specifically, an N-type silicon epitaxial layer 102 is epitaxially grown on a high-concentration N+ type single crystal silicon 101 . A buffer oxide layer 103 is chemically vapor deposited on the surface of the epitaxial layer 102 . A silicon nitride layer 104 is deposited on the buffer oxide layer 103 by a plasma enhanced chemical vapor method. Wherein, the thickness of the epitaxial layer 102 is 9-11 microns, and 10 microns is used in this embodiment. The thickness of the silicon nitride layer 104 is 1.8-2.2 microns, and 2 microns is used in this embodiment. The buffer oxide layer is generally a silicon dioxide layer formed by thermal oxidation of silicon, which a...
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