High electron mobility spin field effect transistor and its preparation method
A field effect transistor and high electron mobility technology, applied in the field of high electron mobility spin field effect transistor and its preparation, can solve the problems of low spin injection efficiency and affecting device performance, so as to improve efficiency and performance Effect
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Embodiment 1
[0047] See figure 1 , figure 1 A flow chart of a method for manufacturing a high electron mobility spin field effect transistor provided in an embodiment of the present invention, wherein the method includes:
[0048] (a) Select 4H-SiC substrate;
[0049] (b) growing N-type Ga on the 4H-SiC substrate 2 o 3 epitaxial layer;
[0050] (c) In the N-type Ga 2 o 3 Fabricate source and drain regions in the epitaxial layer;
[0051] (d) forming electrodes on the surfaces of the source region and the drain region;
[0052] (e) In the N-type Ga 2 o 3 A gate is fabricated on the epitaxial layer to complete the fabrication of the transistor.
[0053] Preferably, before step (b), it also includes:
[0054] The 4H-SiC substrate was ultrasonically cleaned using acetone and alcohol.
[0055] Preferably, step (b) can be:
[0056]Using Ga with a mass fraction of 99.99999% as the evaporation source and Sn with a mass fraction of 99.999% as the dopant source, grow N-type Ga on the 4H...
Embodiment 2
[0085] Please refer to Figure 2a-Figure 2g , Figure 2a-Figure 2g It is a schematic diagram of a preparation method of a high electron mobility spin field effect transistor according to an embodiment of the present invention, and the preparation method includes the following steps:
[0086] Step 1, selecting a substrate 201 . Select 4H-SiC substrate 201, such as Figure 2a shown.
[0087] Step 2, growing Ga on the surface of the 4H-SiC substrate 201 2 o 3 epitaxial layer 202 . Using Ga with a mass fraction of 99.99999% as the evaporation source and Sn with a mass fraction of 99.999% as the doping source, a 4H-SiC substrate with a thickness of 0.4 μm and a doping concentration of 1×10 was grown on the MBE process. 14 -1×10 16 cm -3 N-type Ga 2 o 3 epitaxial layer 202, such as Figure 2b shown.
[0088] Step 3, in N-type Ga 2 o 3 An Al barrier layer 203 is grown on the epitaxial layer 202 . Using CVD process, in Ga 2 o 3 An Al barrier layer 203 with a thickness...
Embodiment 3
[0094] Please refer to image 3 , image 3 A schematic structural diagram of an SOI-based lateral double-channel power solid-state plasma PiN diode provided by an embodiment of the present invention. The luminous tube adopts the above-mentioned Figure 2a-Figure 2g prepared as indicated. Specifically, the diode includes: 4H-SiC substrate 301, N-type Ga 2 o 3 Epitaxial layer 302, source 303, drain 304, gate 305 and SiO 2 isolation layer 306 .
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Abstract
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