Wafer-level back gold chip packaging structure and packaging method thereof

Abstract

The present invention discloses a back gold chip packaging structure and a packaging method thereof, belonging to the technical field of semiconductor packaging. A plurality of chip electrodes and front protective layers are arranged at the front surface of a silicon-based body, each front protective layer is provided with one front protective layer opening to expose chip electrodes again, and metal bump are arranged at the surfaces of the chip electrodes. The back surface of the silicon-based body is provided with a back gold layer, the back gold layer is in bonding connection with the back surface of the silicon-based body through a back gold bonding layer. A plastic packaging layer packages exposed surfaces of the back gold layer and the silicon-based body, and a plastic packaging layeropening is arranged to expose the exposed surface of the back surface of the back gold layer. The wafer-level back gold chip packaging structure and the packaging method thereof are simple in packaging flow, the silicon face processing technology, the back gold technology, the plastic packaging material ablation and the de-bonding technology are completed on a wafer, and therefore, the wafer-level back gold chip packaging structure and the packaging method thereof accord with future development direction of semiconductor manufacturing.

Description

technical field [0001] The invention relates to a packaging structure and a packaging method for a wafer-level gold-backed chip, belonging to the technical field of semiconductor packaging. Background technique [0002] In recent years, Embedded Package has received more and more attention from the industry. Embedded packages often have better thermal management and reliability advantages than other package structures. In this package, the backside of the chip is usually ground and metallized to reduce power loss or improve the heat dissipation performance of the power chip, and is embedded in an IC substrate for final packaging. [0003] In the embedded packaging structure, the metal layer on the back is used as a pole of the device, and usually requires a process that can withstand laser ablation, which puts forward higher requirements for the thickness of the back gold. [0004] At this stage, most of the chip back gold processes use precious metal structures, including...

AI Technical Summary

Problems solved by technology

During the welding process of the small package, its own weight is relatively light, and it is very easy to cause a short circuit failure due to the phenomenon of tin climbing during the welding process, or in the embedded high-density package, the entire package may be damaged due to displacement and contact with other chips. The package is scrapped

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