A method for manufacturing a stacked polysilicon gate structure of a semiconductor device

Abstract

The invention relates to a method for manufacturing a stacked polysilicon gate structure of a semiconductor device, comprising the steps of: forming a trench on a wafer surface; Filling the trench with silicon oxide by deposition; Part of the silicon oxide is etched back; Forming a corner structure at a corner of the top of the groove; Deposition of nitrogenous compounds; Dry etching nitrogen-containing compound, the corner structure surface forms nitrogen-containing compound sidewall residue extending into the groove; A part of silicon oxide is etched off by using the residual nitrogen-containing compound sidewall as a mask; Repeating the above three steps in turn until the silicon oxide in the trench is etched to the desired bottom silicon oxide thickness; Removing nitrogen compounds inthe trench; Filling polysilicon into the trench; Forming an isolated silicon oxide on the polysilicon; The above two steps are repeatedly performed to form a multilayer polysilicon and a silicon oxideisolation. The invention adopts the method of deposition and step etching to form the silicon oxide in the trench, which reduces the oxidation time and improves the production efficiency.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for manufacturing a stacked polysilicon gate structure of a semiconductor device. Background technique [0002] Today's switching power supply operating frequency has been raised to a high frequency above 1MHz. Reduce the feedback capacitance (hereinafter referred to as C GD ) is a major research direction. [0003] At present, for a metal oxide semiconductor field effect transistor (HV MOSFET) with high voltage resistance, a withstand voltage (breakdown voltage) of more than 600 volts can be achieved through a power trench MOS device. One of the implementation methods is to use a stacked-polysilicon gate (Stacked-POLY) structure: multiple layers of polysilicon are formed in deep grooves, and each layer is isolated by a certain thickness of silicon oxide. The polysilicon on the top layer is connected to the gate voltage Vg. Therefore, a coupling capacitance ...

AI Technical Summary

Problems solved by technology

[0004] In a process for forming the above-mentioned stacked polysilicon gate structure, the thickness of the bottom oxide layer is grown by an oxidation process at a higher temperature and a longer time. If a thicker oxide layer needs to be formed on this basis, it will take longer Time oxidation, thus increasing process time and reducing production efficiency

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