A JCD integrated device based on p-type epitaxy and its preparation method

Abstract

The invention relates to a P-type epitaxy-based JCD integrated device and a preparation method thereof, belonging to the technical field of power semiconductor integration. The present invention adopts the following main process steps: prepare substrate; form N+ buried layer; grow P-type epitaxial layer; form punch-through isolation region; prepare field oxygen; N-type region implantation, pushing junction; preparation of gate oxide and polysilicon; N+ implantation; P+ implantation; preparation of ohmic holes; Diodes, Poly capacitors, and well resistors are integrated on the same chip. The invention has good compatibility of high and low voltage devices, good isolation effect and less mask plate times. JFET has the advantages of high-precision analog characteristics, large input impedance, high speed, and good anti-radiation characteristics. It realizes the integration of low-voltage JFET devices, high-voltage control DMOS parts, and low-voltage logic CMOS parts. It can be applied to power management ICs, protection circuits and In the process design of integrated op amp.

Description

technical field [0001] The invention belongs to the technical field of power semiconductor integration, and in particular relates to a P-type epitaxy-based JCD integrated device and a preparation method thereof. Background technique [0002] For more than 40 years, semiconductor technology has continuously reduced the chip feature size along the route of Moore's Law. However, semiconductor technology has developed to a bottleneck: as the line width becomes smaller and smaller, the manufacturing cost increases exponentially; and as the line width approaches At the nanometer scale, the quantum effect is becoming more and more obvious, and the leakage current of the chip is also increasing. Therefore, the development of semiconductor technology must consider the "post-Moore era" issue. In 2005, the international technology roadmap for semiconductors (ITRS for short) proposed the concept of more than Moore. Power semiconductor devices and power integration technology play a ve...

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Problems solved by technology

[0002]For more than 40 years, semiconductor technology has been shrinking the chip feature size along the route of Moore's Law. However, semiconductor technology has developed to a bottleneck: with the increasing line width The smaller the size, the manufacturing cost increases exponentially; and as the line width approaches the nanometer scale, the quantum effect becomes more and more obvious, and the leakage current of the chip becomes larger and larger

However, the integration technology of JFET devices still has many problems such as compatibility and poor performance of JFET devices.

Due to the particularity of the double-gate structure of the JFET device itself, there are still integration issues for the technical personnel to realize the monolithic integration of the low-voltage JFET, the high-voltage control part, and the low-voltage logic part, the compatibility of the high-voltage DMOS and the low-voltage JFET part, and the compatibility of the JFET and CMOS parts. Obstacles, due to the complex manufacturing process of JFET devices, its saturation characteristics and pinch-off characteristics are difficult to meet the application requirements at the same time, resulting in restrictions on the performance of JFET devices and the development of related integrated op amps

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